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(R)
STV82X8
Digital Audio Decoder/Processor for BTSC Television/Video Recorders
PRELIMINARY DATA
Key Features
Fully Automatic Multi-Standard Demodulation M/N standards FM mono BTSC (US MTS) stereo and SAP standards

Multi-Channel Capability 3 IS digital inputs, S/PDIF (in/out) 5.1 analog outputs Dolby(R) Pro Logic(R) Dolby(R) Pro Logic II(R) 2 IS digital outputs (TQFP100 only) 2 asynchronous IS digital inputs (TQFP100 only)

Virtual or true multi-channel capabilities and easy digital links make them ideal for digital audio low cost consumer applications. Starting from enhanced stereo up to independent control of 5 loudspeakers and a subwoofer (5.1 channels), the STV82X8 family offers standard and advanced features plus sound enhancements, spatial and virtual effects to enhance television viewer comfort and entertainment.
Typical Applications
Analog and digital TV with virtual surround sound Analog and digital TV with multi-channel surround sound DVD and HDD recorders "Palm size" portable TV

Sound Processing ST royalty-free processing: ST WideSurround, ST OmniSurround, ST Dynamic Bass, ST Bass Enhancer, SRS(R) WOWTM , SRS(R) TruSurround XTTM which is Virtual Dolby(R) Surround and Virtual Dolby(R) Digital compliant Independent Volume / Balance for Loudspeakers and Headphone Loudspeakers: Smart Volume Control (SVC), 5-band equalizer and loudness Headphone: Smart Volume Control (SVC), basstreble, loudness, ST Dynamic Bass and SRS(R) TruBassTM 3 different bip tones
x8 82 V ST
(R)
ST
2 V8
x8
(R)
TQFP80 Package
TQFP100 Package
Analog Audio Matrix 4 stereo inputs or 5 stereo inputs (TQFP100 only) 3 stereo outputs Pass-thru mode

Audio Delay for Audio Video Synchronization Embedded stereo delay up to 120 ms for lip-sync function Independent delay on headphone and loudspeaker channels External additional audio delay support (TQFP100 only)
(c) 2004 SRS Labs, Inc. All rights reserved, SRS and the SRS logo are registered trademarks of SRS Labs, Inc.
The STV82X8 family, based on audio digital signal processors (DSP), performs high quality and advanced dedicated digital audio processing.These devices provide all of the necessary resources for automatic detection and demodulation of analog audio transmissions for USA, Taiwanese, Brazilian etc. terrestrial analog TV broadcasts.
"Dolby", "Pro Logic", and the double-D symbol are trademarks of Dolby Laboratories.
Rev. 1 February 2005 1/157
CLK_SEL
XTALIN
XTALOUT
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IS Inputs/Output O_PCM_CLK S/PDIF in S/PDIF out
Audio DAC
0.9 VRMS
DATA_0 DATA_1 DATA_2 LR_CLK
IS Interface
S_CLK
IRQ Volume Balance Mute matrix
Audio DAC
0.9 VRMS
Automatic
Headphone Detection
Detection & Smart Control
Loudspeakers Digital Audio Processing Delay, Equalizer, Loudness Dolby(R) Pro Logic(R) Dolby(R) Pro Logic II(R), ST WideSurround, ST Dynamic Bass, ST OmniSurround, ST Bass Enhancer Smart Volume Control, Bass Management, Bip tones SRS(R) WOWTM or TruSurroundTM
LS_L LS_R Loudspeakers LS_C LS_SUB
Sound IF BTSC Digital Decoder
Headphone Digital Audio Processing Volume, Balance, Loudness Smart Volume Control ST Dynamic Bass, Bass/Treble SRS (R) TruBassTM
Audio DAC
Audio Matrix
SIF
AGC
A/D
Back-end Processing and Pre-scaler
Audio DAC
0.9 VRMS
Mono Input MONO_IN
HP_LSS_L HP_LSS_R Headphone / Surround
2VRMS
SC1_IN_L SC1_IN_R
Audio A/D
Figure 1: STV82X8 Block Diagram (TQFP80)
SC2_IN_L SC2_IN_R
SC1_OUT_L SC1_OUT_R
SC3_IN_L SC3_IN_R
Input Analog Audio Matrix
SC4_IN_L SC4_IN_R Clock Generator
Output Analog Audio Matrix
2VRMS
SC2_OUT_L SC2_OUT_R
IC Interface
2VRMS
SCART Inputs SDA
SC3_OUT_L SC3_OUT_R SCART Outputs
SCL
STV82X8
IC
STV82X8
A_DATA IS Inputs/Outputs IS Outputs PCM_CLK O_SCLK O_LR_CLK O_DATA_1 O_DATA_0 S/PDIF in S/PDIF out
Audio DAC
0.9 VRMS
SCLK
DATA_0 DATA_1 DATA_2 LR_CLK
A_LR_CLK
A_S_CLK
D_DATA
Loudspeakers Digital Audio Processing Delay, Equalizer, Loudness Dolby(R) Pro Logic(R) Dolby(R) Pro Logic II(R), ST WideSurround, ST Dynamic Bass, ST OmniSurround, ST Bass Enhancer Smart Volume Control, Bass Management, Bip tones SRS(R) WOWTM or TruSurround XTTM
IS interface
IRQ Volume Balance Mute matrix
Audio DAC
0.9 VRMS
Automatic
Headphone Detection
Detection & Smart Control
LS_L LS_R Loudspeakers LS_C LS_SUB
Audio Matrix
Sound IF SIF1 BTSC Digital Decoder
Headphone Digital Audio Processing Delay,Bass/Treble, Loudness, Smart Volume Control, ST Dynamic Bass, Bip tones SRS(R) TrubassTM,
Audio DAC
SIF2
AGC
A/D
Back-end Processing and Pre-scaler
Audio DAC
0.9 VRMS
Mono Input MONO_IN Audio A/D
HP_LSS_L HP_LSS_R Headphone / Surround
2VRMS
SC1_IN_L SC1_IN_R
Figure 2: STV82X8 Block Diagram (TQFP100)
SC2_IN_L SC2_IN_R
SC1_OUT_L SC1_OUT_R
SC3_IN_L SC3_IN_R
Input Analog Audio Matrix
SC4_IN_L SC4_IN_R Clock Generator
Output Analog Audio Matrix
2VRMS
SC2_OUT_L SC2_OUT_R
SC5_IN_L SC5_IN_R
IC Interface
2VRMS
SCART Inputs SDA
SC3_OUT_L SC3_OUT_R SCART Outputs
SCL IC
CLK_SEL
XTALIN
XTALOUT
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STV82X8
Table of Contents
Chapter 1
1.1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
STV82X8 Overview ............................................................................................................ 13
1.1.1 Core Features ..........................................................................................................................................13 1.1.2 Software Information ...............................................................................................................................14 1.1.3 Electrical Features ...................................................................................................................................14
1.2
Typical Applications ........................................................................................................... 15
Chapter 2 Chapter 3
3.1 3.2
System Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Digital Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Sound IF Signal .................................................................................................................. 19 Demodulation ..................................................................................................................... 19
Chapter 4
4.1 4.2 4.3 4.4 4.5 4.6
Dedicated Digital Signal Processor (DSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Back-end Processing ......................................................................................................... 21 Audio Processing ............................................................................................................... 22 ST WideSurround ............................................................................................................... 24 ST OmniSurround .............................................................................................................. 25 Dolby Pro Logic II Decoder ................................................................................................ 25 Bass Management ............................................................................................................. 25
4.6.1 Bass Management Configuration 0 .........................................................................................................26 4.6.2 Bass Management Configuration 1 .........................................................................................................26 4.6.3 Bass Management Configuration 2 .........................................................................................................27 4.6.4 Bass Management Configuration 3 .........................................................................................................28 4.6.5 Bass Management Configuration 4 .........................................................................................................29
4.7
SRS WOW and TruSurround XT ...................................................................................... 29
4.7.1 SRS TruSurround ....................................................................................................................................29 4.7.2 SRS WOW ...............................................................................................................................................30
4.8 4.9 4.10 4.11 4.12 4.13 4.14 4.15
Smart Volume Control (SVC) ............................................................................................. 30 ST Dynamic Bass/ST Bass Enhancer ............................................................................... 31 5-Band Audio Equalizer ..................................................................................................... 31 Bass/Treble Control ........................................................................................................... 31 Automatic Loudness Control .............................................................................................. 32 Volume/Balance Control .................................................................................................... 32 Soft Mute Control ............................................................................................................... 33 Beeper ................................................................................................................................ 33
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STV82X8 Chapter 5 Chapter 6
6.1
Analog Audio Matrix (Input / Output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 IS Interface (In / Out) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
IS Inputs ............................................................................................................................ 36
6.1.1 IS Inputs in TQFP 80 Package ...............................................................................................................36 6.1.2 IS Inputs in TQFP 100 Package .............................................................................................................37
6.2
IS Outputs ......................................................................................................................... 37
6.2.1 IS Outputs in TQFP 80 Package ............................................................................................................37 6.2.2 IS Outputs in TQFP 100 Package ..........................................................................................................38
Chapter 7 Chapter 8
8.1
S/PDIF Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Power Supply Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Standby Mode (Loop-through mode) ................................................................................. 41
Chapter 9
9.1 9.2 9.3
Additional Controls and Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Headphone Detection ........................................................................................................ 42 IRQ Generation .................................................................................................................. 42 IC Bus Expander ............................................................................................................... 42
Chapter 10 Chapter 11
11.1 11.2
STV82X8 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 IC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
IC Address and Protocol ................................................................................................... 44 Start-up and Configuration Change Procedure .................................................................. 45
Chapter 12
12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 12.10
Register List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
IC Register Map ................................................................................................................ 47 Software Registers ............................................................................................................. 49 STV82X8 General Control Registers .................................................................................. 53 Clocking 1 .......................................................................................................................... 56 Demodulator ....................................................................................................................... 58 Demodulator Channel 1 ..................................................................................................... 61 I2S and Analog Control ...................................................................................................... 69 Clocking 2 .......................................................................................................................... 72 DSP Control ....................................................................................................................... 73 Automatic Standard Recognition ........................................................................................ 78
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STV82X8
12.11 12.12 12.13 12.14 12.15 12.16 12.17 12.18 12.19 12.20 Demodulator ....................................................................................................................... 81 Audio PreProcessing & Selection ...................................................................................... 84 Matrixing ............................................................................................................................. 89 Audio Processing ............................................................................................................... 96 Mute ................................................................................................................................. 123 Beeper .............................................................................................................................. 124 SPDIF Output Configuration ............................................................................................ 126 Headphone Configuration ................................................................................................ 126 DAC Control ..................................................................................................................... 127 AutoStandard Coefficients Settings ................................................................................. 129
Chapter 13
13.1 13.2
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
TQFP 80-pin Package ...................................................................................................... 131 TQFP 100-pin Package .................................................................................................... 134
Chapter 14 Chapter 15 Chapter 16
16.1 16.2 16.3 16.4 16.5 16.6 16.7 16.8 16.9 16.10 16.11 16.12 16.13 16.14
Application Diagrams
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
Input/Output Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
Absolute Maximum Ratings ............................................................................................ 145 Thermal Data .................................................................................................................. 145 Power Supply Data .......................................................................................................... 145 Crystal Oscillator ............................................................................................................. 146 Analog Sound IF Signal .................................................................................................. 146 SIF to IS Output Path Characteristics ............................................................................. 146 SCART to SCART Analog Path Characteristics .............................................................. 147 SCART and MONO IN to IS Path Characteristics .......................................................... 148 I2S to LS/HP/SUB/C Path Characteristics ....................................................................... 148 IS to SCART Path Characteristics .................................................................................. 148 MUTE Characteristics ...................................................................................................... 149 Digital I/Os Characteristics ............................................................................................... 149 IC Bus Characteristics .................................................................................................. 150
IS Bus Interface .............................................................................................................. 151
Chapter 17
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Package Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153
STV82X8
17.1 17.2 TQFP80 Package ............................................................................................................ 153 TQFP100 Package .......................................................................................................... 154
Chapter 18
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155
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General Description
STV82X8
1
General Description
This chip performs BTSC stereo and SAP analog TV stereo sound identification and demodulation (no specific IC programming is required). It offers various audio processing functions such as equalization, loudness, beeper, volume, balance, and surround effects. It provides a cost-effective solution for analog and digital TV designs. The STV82X8 is an audio processor which integrates SRS(R) WOWTM, SRS(R) TruSurround XTTM, Dolby(R) Pro Logic(R), Dolby(R) Pro Logic II(R), Virtual Dolby(R) Surround (VDS) and Virtual Dolby(R) Digital (VDD) capabilities. Advanced ST royalty-free algorithms such as ST OmniSurround, ST WideSurround, ST Dynamic Bass, ST Bass Enhancer are also available in this audio sound processor. ST OmniSurround is a certified Dolby(R) algorithm for the Virtual Dolby(R) Digital (VDD) and the Virtual Dolby(R) Surround (VDS). When using VDD or VDS, either an external Dolby(R) Digital or an internal Pro Logic(R) (or Pro Logic II(R)) decoder must be used respectively. The STV82X8 is perfectly suited to current and future digital TV platforms, based on audio/video digital chips (STD2000 - DTV100 platform) which include an internal digital decoder (MPEG, Dolby(R) Digital...). In the case where a Dolby(R) Digital decoder is embedded in the audio/video digital chip, Virtual Dolby(R) Digital certification could be obtained.
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STV82X8
General Description
Table 1: STV82X8 Version List (TQFP 80)
STV8248 S T V 8 2 1 8 S T V 8 2 3 8 S T V 8 2 4 8 D S X STV8258 S T V 8 2 5 8 D S T V 8 2 5 8 D S X STV8268 S T V 8 2 6 8 D S X STV8278 S T V 8 2 7 8 D S X STV8288 S T V 8 2 8 8 D S X
S T V 8 2 4 8 D
S T V 8 2 6 8 D
S T V 8 2 7 8 D
S T V 8 2 8 8 D
Multi-Channel Capabilities IS data input number Analog loudspeakers output number
1 2.1 1 2.1 1 2.1 1 2.1 3 2.1 3 2.1 1 5.1 1 5.1 3 5.1 3 5.1 3 5.1 3 5.1
Embedded SRS(R) and Dolby(R) algorithms Dolby(R) Pro Logic (R) (DPLI) or Dolby(R) Pro Logic II(R) (DPLII) SRS(R) WOWTM (WOW) or SRS(R) TruSurround XTTM (XT) General Capabilities S/PDIF Pass-thru BTSC & SAP / Mono FM Demodulation ST OmniSurround1, ST WideSurround ST Voice, ST Dynamic Bass, ST Bass Enhancer Dolby(R) Pro Logic (R) (DPLI) or Dolby(R) Pro Logic II(R) (DPLII) 5.1 output Dolby(R) Digital Bypass 5.1 output2 Virtual Dolby(R) Surround Virtual Dolby(R) Digital capability2
X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X WOW DPLI DPLI DPLI DPLI DPLI DPLI DPLI DPLI DPLII DPLII
XT
XT
XT
XT
XT
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
DPLI
DPLI
DPLI
DPLI
DPLII
DPLII
X X X
X X X
X X X
X X X
1. When using Virtual Dolby(R) Digital or Virtual Dolby(R) Surround with ST OmniSurround or SRS(R) TruSurround XTTM a Dolby(R) Digital or a Pro Logic (R) (or Pro Logic II(R)) decoder is mandatory respectively 2. Dolby(R) Digital Bypass capability or Virtual Dolby(R) Digital are obtained with the use of an external Dolby(R) Digital decoder (for example STD2000).
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General Description
Figure 3: Package Ordering Information
STV82X8
Order Code: STV82X8 (Tray) STV82X8/T (Tape & Reel) For Example: STV8258DSX/T will be delivered in Tape & Reel conditioning
FP TQ
80
(R)
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STV82X8
General Description
Table 2: STV82X8 Version List (TQFP 100)
STV8248 S T V 8 2 1 8 F S T V 8 2 3 8 F S T V 8 2 4 8 F D S X STV8258 S T V 8 2 5 8 F D S T V 8 2 5 8 F D S X STV8268 S T V 8 2 6 8 F D S X STV8278 S T V 8 2 7 8 F D S X STV8288 S T V 8 2 8 8 F D S X
S T V 8 2 4 8 F D
S T V 8 2 6 8 F D
S T V 8 2 7 8 F D
S T V 8 2 8 8 F D
Multi-Channel Capabilities IS data input number Analog loudspeakers output number
1 2.1 1 2.1 1 2.1 1 2.1 3 2.1 3 2.1 1 5.1 1 5.1 3 5.1 3 5.1 3 5.1 3 5.1
Embedded SRS(R) and Dolby(R) algorithms Dolby(R) Pro Logic (R) (DPLI) or Dolby(R) Pro Logic II(R) (DPLII) SRS(R) WOWTM (WOW) or SRS(R) TruSurround XTTM (XT) General Capabilities S/PDIF Pass-thru Second SIF input IS Output (always available) BTSC & SAP / Mono FM Demodulation ST OmniSurround1, ST WideSurround ST Voice, ST Dynamic Bass, ST Bass Enhancer Dolby(R) Pro Logic (R) (DPLI) or Dolby(R) Pro Logic II(R) (DPLII) 5.1 output Dolby(R) Digital Bypass 5.1 output2 Virtual Dolby(R) Surround Virtual Dolby(R) Digital capability2
X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X WOW DPLI DPLI DPLI DPLI DPLI DPLI DPLI DPLI DPLII DPLII
XT
XT
XT
XT
XT
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
DPLI
DPLI
DPLI
DPLI
DPLII
DPLII
X X X
X X X
X X X
X X X
1. When using Virtual Dolby(R) Digital or Virtual Dolby(R) Surround with ST OmniSurround or SRS(R) TruSurround XTTM a Dolby(R) Digital or a Pro Logic (R) (or Pro Logic II(R)) decoder is mandatory respectively 2. Dolby(R) Digital Bypass capability or Virtual Dolby(R) Digital are obtained with the use of an external Dolby(R) Digital decoder (for example STD2000).
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General Description
Figure 4: Package Ordering Information
STV82X8
Order Code: STV82X8F (Tray) STV82X8F/T (Tape & Reel) For Example: STV8258FDSX/T will be delivered in Tape & Reel conditioning
TQ
0 10 FP
(R)
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STV82X8
General Description
1.1
1.1.1
STV82X8 Overview
Core Features
Single audio source processing: -- IF source and/or analog stereo input (SCART) -- one digital source with a maximum of 6 synchronous channels (5.1 is obtained across three IS)

SIF input signal with Automatic Gain Control (AGC) BTSC and SAP demodulator, FM Mono Audio processor working at 48 kHz with specific features: -- For loudspeakers (L, R, LS, RS, SubW, C): Dolby(R) Pro Logic II (R) decoder with bass management SRS(R) WOWTM or TruSurround XTTM including Virtual Dolby(R) Surround and Virtual Dolby(R) Digital ST WideSurround ST OmniSurround ST Dynamic Bass / ST Bass Enhancer 5-band equalizer or bass / treble controls Loudness Smart Volume Control Volume/balance/soft-mute Three different types of bips Video processing delay compensation -- For headphones: SRS(R) TruBassTM ST Dynamic Bass Smart Volume Control Bass / treble controls Loudness Volume/balance/soft-mute Three different types of bips Video processing delay compensation

Shared outputs for headphone and certain loudspeakers (surround channels); Analog matrix with: -- Five external inputs: Four SCART inputs (2 VRMS capable) One analog mono input (0.5 VRMS) -- One internal input from a digital matrix via a DAC -- Three external outputs (2 VRMS capable) -- One internal output for the digital matrix (using an internal ADC)
Digital matrix with: -- Three input modes (demodulator/SCART, SCART only and IS) -- Three stereo outputs (loudspeakers, headphone and SCART)

High-end audio DAC S/PDIF output for connection with an external amplifier/decoder Internal multiplexer for the S/PDIF output (to share the internal S/PDIF output and the S/PDIF output generated by the external decoder of the digital broadcast)
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General Description

STV82X8
Specific stand-by mode (loop-through) Control by IC bus (two IC addresses) System PLL and clock generation using either a single crystal oscillator or a differential clock input
1.1.2
Software Information
The different software combinations are listed in Table 3.
Table 3: Input/Output Software Configurations
Output (Number of Channels)
Input (Number of Channels) 2 (+1) 1 (Mono) ST WideSurround or SRS(R) WOWTM ST WideSurround or ST OmniSurround or SRS(R) TruSurround XTTM or SRS(R) WOWTM or Dolby(R) Pro Logic(R) II ST WideSurround or ST OmniSurround or SRS(R) TruSurround XTTM or SRS(R) WOWTM or Dolby(R) Pro Logic(R) I or II ST OmniSurround or SRS(R) TruSurround XTTM ST OmniSurround or SRS(R) TruSurround XTTM 4 (+1) 5.1
2 (LO & RO)
Dolby(R) Pro Logic(R) II
Dolby(R) Pro Logic(R) II
2 (LT & RT)
Dolby(R) Pro Logic(R) I or II
Dolby(R) Pro Logic(R) II
4 (+1) 5.1
No processing Downmix No processing
Note: Note:
In addition to the above sound processing, it is always possible to add ST Voice and also ST Dynamic Bass or ST Bass Enhancer algorithms. The SRS(R) TruSurround(R) and ST OmniSurround are approved by Dolby Labs as Virtual Dolby Surround (VDS) and Virtual Dolby Digital (VDD). The SRS(R) TruSurround XTTM system is composed of:

SRS(R) TruSurroundTM SRS(R) WOWTM
The SRS(R) WOWTM system also includes:

SRS(R) Dialog ClarityTM SRS(R) TruBassTM SRS(R) 3D mono / stereo
1.1.3
Electrical Features
Multi Power Supplies: 1.8 V, 3.3 V and 8 V. Power Consumption:

lower than 800mW in functional mode (full features) 200 mW in loop-through mode corresponding to the switch-off of all digital blocks
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STV82X8
General Description
1.2
Typical Applications
The STV82X8 is specified to enable flexible, analog and digital TV chassis design (refer to Figure 5, Figure 6, Figure 7 and Figure 8). The main considerations are:

all necessary connections between devices can be provided through the TV set, pseudo stand-by mode used to copy to VCR or the DVD sources when the TV set is OFF, pin compatibility with previous STV82x7 (TQFP80 package) TV design.
The STV82X8 can be used to process dual audio sources (one analog and one digital in parallel). Note: Headphone and loudspeakers can be used simultaneously for dual-language purpose. In this case, certain restrictions occur (see Section 4.2: Audio Processing). For more connections, the SCART-to-SCART path can be used. The use of these full analog paths implies that the sound is not digitally processed.
Figure 5: STV8238 Typical Application (Enhanced Stereo)
Tuner
IS In and Out (TQFP100) S/PDIF IS In or Out (TQFP80) Output & Pass-thru
R
STV8238
or Demodulation - BTSC stereo & SAP Sound Processing - Volume, Balance, 5-Band Equalizer - ST OmniSurround - SRS(R) WOWTM
SubW
L
4 x SCART (TQFP100) Left Right
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General Description
Figure 6: STV8248 Typical Application (Analog Virtual Sound)
STV82X8
IS In and Out (TQFP100) IS In or Out (TQFP80) Tuner
S/PDIF Output & Pass-thru
R
STV8248
or Demodulation - BTSC stereo & SAP Sound Processing - Volume, Balance, 5-Band Equalizer - SRS(R) TruSurround XTTM - ST OmniSurround - Virtual Dolby(R) Surround1 SubW
L
4 x SCART (TQFP100) Left Right
1. When using VDS with ST OmniSurround or SRS TruSurround XTTM, an optional internal Pro Logic(R) decoder is mandatory.
Figure 7: STV8258 Typical Application (Digital: Virtual Sound)
Multi-Channel Digital Decoder (Dolby(R) Digital)
R S/PDIF Output & Pass-thru SubW
IS
Tuner
STV8258
Demodulation - BTSC stereo & SAP Audio Processing - Volume, Balance, 5-Band Equalizer - SRS(R) TruSurround XTTM - ST OmniSurround - Virtual Dolby(R) Surround1 - Virtual Dolby(R) Digital2
or
L
4 x SCART (TQFP100) Left Right
1. When using VDS with ST OmniSurround or SRS TruSurround XTTM, an optional internal Pro Logic(R) decoder is mandatory. 2. When using VDD with ST OmniSurround or SRS TruSurround XTTM, an external Dolby(R) Digital decoder is mandatory.
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STV82X8
General Description
Figure 8: STV8288 Typical Application (Digital TV: Multi-Channel and Virtual Sound)
Multi-Channel Digital Decoder (Dolby(R) Digital)
IS
Tuner
S/PDIF Output & Pass-thru
R
SubW
RS C LS L
STV8288
Demodulation - BTSC stereo & SAP Audio Processing - Volume, Balance, 5-Band Equalizer - Dolby(R) Pro Logic II(R) - ST OmniSurround - 5.1 Analog Outputs - SRS(R) TruSurround XTTM - Virtual Dolby(R) Surround1 - Virtual Dolby(R) Digital2
or
4 x SCART (TQFP100)
Left Right Shared with surround LS/RS
1. When using VDS with ST OmniSurround or SRS TruSurround XTTM, an optional internal Pro Logic(R) decoder is mandatory. 2. When using VDD with ST OmniSurround or SRS TruSurround XTTM, an external Dolby(R) Digital decoder is mandatory.
Figure 9: STV8218 Typical Application (DVD & HDD Recorders)
A/V Codec (Digital Recorder)
Tuner
IS
or
STV8218
Demodulation - BTSC stereo & SAP - Volume, Balance, 5-Band Equalizer - ST OmniSurround
4 x SCART (TQFP100) Left Right
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System Clock
STV82X8
2
System Clock
The System Clock integrates 2 independent frequency synthesizers. The first frequency synthesizer is used by the demodulator at a frequency of 24.576 MHz. The second frequency synthesizer is used by the DSP core and can be adjusted between 100 and 150 MHz depending on the application. The default values are designed for a standard 27-MHz reference frequency provided by a stable single crystal oscillator or an external differential clock signal (for example, from the STV35x0) depending on the CLK_SEL pin configuration (CLK_SEL = 1 means a single crystal oscillator, 0 means an external differential clock). The 27-MHz value is the recommended frequency for minimizing potential RF interference in the application. The sinusoidal clock frequency, and any harmonic products, remain outside the TV picture and sound IFs (PIF/SIF) and Band-I RF.
Note:
A change in the reference frequency is compatible with other default IC programming values, including those of the built-in Automatic Standard Recognition System.
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STV82X8
Digital Demodulator
3
Digital Demodulator
The Digital Demodulator (see Figure 10) consists of a channel demodulator and a stereo/SAP decoder. All channel parameters are programmed automatically by the built-in Automatic Standard Recognition System (Autostandard) in order to find the STEREO or the SAP modes. Channel parameters can also be programmed manually via the IC interface for very specific standards not included among the known standards.
Figure 10: Demodulator Block Diagram
DSP Processing
DEMOD_STAT(0Dh) STEREO_SAP_STATUS(4Ch) ACOEFF1(1Dh) CARFQ1 (12-14h) FIR1C (15-1Ch) BCOEFF1(1Eh) SAP_CONF(47h) AUTOSTD DETECTION
SIF
AGC Amp
A/D
DCO1+ Mixer
Channel Filter FIR1
FM Demodulator
Stereo/SAP Demodulator
(L+R)* or mono* (L-R)dbx or SAPdbx
Deemphasis, DBX decoding and dematrixing
AGC Control *: Pre-emphasis signal dbx: DBX -encoded signal
3.1
Sound IF Signal
The Analog Sound Carrier IF is connected to the STV82X8 via the SIF pin. Before Analog-to-Digital Conversion (ADC), an Automatic Gain Control (AGC) is performed to adjust the incoming IF signal to the full scale of the ADC. A preliminary video rejection is recommended to optimize conversion and demodulation performances. The AGC system provides a gain value allowing for a wide range of SIF input levels. The TQFP100 package provides a second SIF input.
3.2
Demodulation
The demodulation system operates by default in Automatic mode. In this mode, the STV82X8 is able to identify and demodulate the BTSC TV sound standard including stereo and SAP modes without any external control via the IC interface. The built-in Automatic Standard Recognition System (Autostandard) automatically programs the appropriate bits in the IC registers which are forced to Read-only mode for users. STEREO and SAP modes can be removed (or added) from the List of modes to be recognized by programming registers AUTOSTD_CTRL. The identified standard is displayed in register AUTOSTD_STATUS and any change to standard is flagged to the host system via pin IRQ. This flag
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Digital Demodulator
STV82X8
must be reset by re-programming the LSB of register IRQ_STATUS while checking the detected standard status by reading registers AUTOSTD_STATUS. ITo recover out-of standard FM deviations or the Sound Carrier Frequency Offset, additional IC controls are provided without interfering with the Automatic Standard Recognition System (Autostandard).
Table 4: BTSC Standard Aural Carrier (4.5 MHz) Peak Deviation
25 kHz (1) 0Fh L-R 2nd Channel 0.05 -15 kHz 0.05 -15 kHz DBX Compression DBX Compression 2Fh 5Fh AM DSB SC FM 10 kHz 5 kHz 50 kHz(1) 15 kHz
Source
Modulation
Frequency Range
Audio Preprocessing
Sub-Carrier
Modulation Type
Sub-Carrier Deviation
Monophonic Pilot Stereophonic SAP
L+R
0.05 -15 kHz
75 s Preemphasis
(1) L+R and L-R must not exceed 50 kHz Sound Carrier Frequency Offset Recovery:IF Carrier frequency can be adjusted with register CAROFFSET1 within a large range (up to 120 kHz ) while the Automatic Standard Recognition System remains active. The frequency offset estimation is written in registers DEMOD_DC_LEVEL and can be used to implement the Automatic Frequency Control (AFC) via an external I2C control. Manual Mode: If required, the Automatic Standard Recognition System system can be disabled (Manual mode) and the user can control all registers including those only controlled by the Automatic Standard Recognition System function when active. Manual mode is selected in register AUTOSTD_CTRL by setting to 0 bits SAP_CHECK, STEREO_CHECK and MONO_CHECK.
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STV82X8
Dedicated Digital Signal Processor (DSP)
4
Dedicated Digital Signal Processor (DSP)
A dedicated Digital Signal Processor (DSP) takes charge of all audio processing features and the low frequency signal processing features of the demodulator. The internal 24-bit architecture will ensure a high quality signal treatment and an excellent dynamic.
4.1
Back-end Processing
The "back-end" processing corresponds to the low frequency signal processing (32 kHz or higher frequencies) of the demodulator and other inputs (IS, ADC). Figure 11 shows a flowchart of the back-end processing tasks. However, the figure shows that the processing is only a SINGLE SOURCE PROCESSING flow (no processing is possible with "Demod + SCART" and IS inputs simultaneously) and that the selection of a headphone output restricts the loudspeakers configuration to 2.1 instead of 5.1.
Figure 11: Back-end Audio Processing
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Dedicated Digital Signal Processor (DSP)
The main features depend on the path:
STV82X8
FM Channel -- DC Removal -- Prescaling -- De-emphasis (50 or 75 us) -- Stereo Dematrix
Input SCART Channel -- DC Removal -- Prescaling
Input IS Channel -- IS Prescaling Digital Audio Matrix -- Audio Channel Multiplexer between the different sources (IF, IS, SCART) towards all outputs (S/PDIF, LS, HP or SCART).
Autostandard management -- device configuration depending on the standard to be detected -- freeze the device when a standard is detected -- once a standard detected, check that there is no change in the detection status -- set the correct action depending on any change in the detection status (mono backup or mute setup and new standard detection)
SCART -- Downmixing: LT / RT or L0 / R0 (see AC-3 specification) -- Soft Mute
4.2
Audio Processing
The following software is provided for main loudspeakers (L, R, C, LS, RS, SubW):

Downmix Dolby(R) Pro Logic II(R) Decoder (LT, RT L, R, C, Ls, Rs, SubW) with Bass Management ST WideSurround, ST OmniSurround, SRS(R) WOWTM or SRS(R) TruSurround XT(R) (certified
Virtual Dolby(R) Surround and Virtual Dolby(R) Digital)

ST Dynamic Bass and ST Bass Enhancer Smart Volume Control (SVC) 5-band Equalizer or Bass-Treble Loudness Volume with independent channels (Smooth Volume Control) Master Volume Control Mute/soft-mute Balance Beeper Pink Noise Generator (used to position the loudspeakers) Programmable Delay for each loudspeaker Adjustable Delay for "lip sync" up to 120 ms (to compensate for audio/video latency)
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STV82X8
Dedicated Digital Signal Processor (DSP)
The following software is provided for the headphone or auxiliary output:

Downmix SRS(R) TruBassTM ST Dynamic Bass Smart Volume Control (SVC) Bass/Treble Loudness Independent Volume for each channel (Smooth Volume Control) Soft Mute Balance Beeper Adjustable Delay for "lip sync" feature up to 120 ms (to compensate for audio/video latency)
The following software is provided for SCART or S/PDIF outputs:

Downmix Soft Mute
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Dedicated Digital Signal Processor (DSP)
STV82X8
Figure 12: Audio Processing for Loudspeakers, Headphone, SCART and S/PDIF outputs
4.3
ST WideSurround
STV82X8 offers three preset ST WideSurround Sound effects on the Loudspeakers path:

Music, a concert hall effect Movie, for films on TV Simulated Stereo, which generates a pseudo-stereo effect from mono source
"ST WideSurround Sound" is an extension of the conventional stereo concept which improves the spatial characteristics of the sound. This could be done simply by adding more speakers and coding more channels into the source signal as is done in the cinema, but this approach is too costly for
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STV82X8
Dedicated Digital Signal Processor (DSP)
normal home use. The ST WideSurround system exploits a method of phase shifting to achieve a similar result using only two speakers. It restores spatiality by adding artificial phase differences. The Surround/Pseudo-stereo mode is automatically selected by the Automatic Standard Recognition System (Autostandard) depending on the detected stereo or mono source. By default, "Movie" is selected for Surround mode. This value may be changed to "Music" by the WIDESRND_MODE bit in the WIDESRND_CONTROL register. Additional user controls are provided to better adapt the spatial effect to the source. The ST WideSurround Gain (WIDESRND_LEVEL) and ST WideSurround Frequency (WIDESRND_FREQ) registers can be used to enhance Music Predominancy in Music mode and Theater effect and Voice Predominancy in Movie mode.
4.4
ST OmniSurround
STV82X8 offers a spatial virtualizer to output any multi-channel input in stereo on the Loudspeakers path. "ST OmniSurround" will recreate a multi-channel spatial sound environment using only the Left and Right front speakers. It can be adapted to any input configuration (OMNISRND_INPUT_MODE). ST Voice will allow you to enhance the voice content of your program to increase the intellegibility and the presence of the sound.
4.5
Dolby Pro Logic II Decoder
Dolby(R) Pro Logic II(R) is a matrix decoder that decodes the five channels of surround sound that have been encoded onto the stereo sound tracks of Dolby(R) Surround program material such as DVD movies and TV shows. It is even possible to decode standard stereo signals like music or non encoded movies. Furthermore, it is an active process designed to enhance sound localization through the use of very high-separation decoding techniques. The Dolby(R) Pro Logic II(R) decoder is also able to emulate the former Dolby(R) Pro Logic(R) decoder in a specific mode.
4.6
Bass Management
This processing will generate the subwoofer signal and adjust all loudspeakers channels gain and bandwidth. Speakers capable of reproducing the entire frequency range will be referred to as "full range speakers", then signals sent to full range speaker will be full bandwidth (no filtering). Speakers that have limited bass handling capabilities will be referred to as "satellite speakers", then signals sent to satellite speaker will be high-pass filtered to remove bass information below 100 Hz. In the STV82X8, five output configuration modes have been implemented according to "Dolby Digital Consumer Decoder" specifications. They are described below.
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Dedicated Digital Signal Processor (DSP) 4.6.1 Bass Management Configuration 0
STV82X8
In some cases, the bass management filters are available in the decoder itself, so there is no need to reproduce these filters. The output configuration shown in Figure 13 offers this possibility.
Figure 13: Bass Management Configuration 0 (with Pro Logic switch indicating its reset state) L L
R
R
C
C
Ls
Ls
Rs -15 dB LFE -5 dB +
Rs
SubW
4.6.2
Bass Management Configuration 1
Configuration 1, shown in Figure 14, assumes that all five speakers are not full range and that all of the bass information will be redirected to and reproduced by a single subwoofer. This configuration is intended for use with 5 satellite speakers. To prevent signal overload, the five main channels are attenuated by 15 dB, while the LFE channel is attenuated by 5dB to maintain the proper mixing ratio.
Figure 14: Bass Management Configuration 1 (with Pro Logic switch indicating its reset state) L
L
R
R
C
C
Ls
Ls
Rs -15 dB LFE -5 dB +
Rs
SubW
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STV82X8 4.6.3 Bass Management Configuration 2
Dedicated Digital Signal Processor (DSP)
Configuration 2 assumes that the left and right speakers, are full range while the center and surround speakers are smaller speakers. Also, all bass data is redirected to the left and right speakers. This configuration include output level adjustment that allows 12 dB attenuation for the 3 smaller speakers (C, Ls, Rs). When the level adjustment will be disabled the decoder boosts by 12 dB the full range speakers (Left, Right).
Figure 15: Bass Management Configuration 2 (all switches indicate their reset state)
Level Adjustment OFF Switch L -12 dB + -1.5 dB C -12 dB C R +12 dB -1.5 dB Ls -12 dB + Rs -15 dB LFE -5 dB + SubW -12 dB Rs Subwoofer ON Switch Ls L
+12 dB
R
-12 dB
+
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Dedicated Digital Signal Processor (DSP) 4.6.4 Bass Management Configuration 3
STV82X8
The third configuration, shown in Figure 16, assumes that all speakers except the center are full range, then all bass information will be directed to and reproduced by the front left and front right and both surround speakers. In order to provide more flexibility to this configuration, a switch will offer an option which will produce a subwoofer channel by the LFE channel. When the Subwoofer Switch is OFF, the input channels will be attenuated by 8 dB. Configuration 3 is required in certain high-end products.
Figure 16: Bass Management Configuration 3 (all switches indicate their reset state) Level Adjustment OFF Switch + L
L
-8dB -4dB
+
+8dB +4dB +8dB +4dB
C
C
-8dB -4dB -4.5dB
R
-8dB -4dB
+
+
+8dB +4dB + +8dB +4dB + +8dB +4dB
R
Ls
Ls
-8dB -4dB -8dB -4dB
Rs
Rs
LFE
-8dB -4dB Subwoofer ON Switch Subwoofer ON Switch +10dB SubW
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STV82X8 4.6.5 Bass Management Configuration 4
Dedicated Digital Signal Processor (DSP)
This configuration implements the Simplified Dolby configuration. The center, left surround and right surround channels are summed and then filtered by the LPF. The composite bass information is either summed back into the left and right channels or summed with the LFE channel and sent to the subwoofer output, see Figure 17.
Figure 17: Implementation of the Bass Management Configuration 4 (Simplified Configuration)
L
+
L
C
C
R
+
R
Ls
Ls
Rs -4.5dB Subwoofer ON Switch -10.5dB -5dB +
Rs
+
LFE
SubW
4.7
SRS WOW and TruSurround XT
The SRS(R) TruSurround XTTM is a processing system that can accept from 1 to 6 channels on input and that will generate a 2-channel output signal. This processing system includes the latest SRS(R) algorithms:

SRS(R) WOWTM SRS(R) TruSurround(R) (Multi-channel signal virtualizer)
4.7.1
SRS TruSurround
The SRS(R) TruSurround(R) is a processing that can accept from 2 to 5 channels on input and that will generate a 2-channel output signal. SRS(R) TruSurround(R) uses Head-Related Transfer Function (HRTF) -based frequency tailoring of (L/R) difference signals to extend the sound image out past the physical boundaries of the speaker placements to surround channel information. These rear channel HRTF curves have much greater peak to valley differences at center frequencies. These were chosen to cause rear channel difference signals to virtualize farther behind the listener and directed to a different virtual position as compared to front channel signals. Information that is equal (L+R) in the rear surround channels
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Dedicated Digital Signal Processor (DSP)
STV82X8
is processed by an identical HRTF curve but mixed in at a much lower amount. This HRTF processing of equal (L/R) signals was again used to virtualize information to the rear of the listener. The SRS(R) TruSurround(R) is certified by Dolby Laboratories to be a Virtual Dolby(R) Digital and Virtual Dolby(R) Surround.
4.7.2
SRS WOW
The SRS(R) WOWTM is an a sound processing system including:

SRS(R) 3D Mono/StereoTM SRS(R) Dialog ClarityTM SRS(R) TruBassTM
4.7.2.1 SRS 3D Mono/Stereo This system is used to create a pseudo-stereo signal for mono inputs or a three-dimensional spatial signal for stereo inputs. 4.7.2.2 SRS Dialog Clarity This system is used to enhance dialog perception. 4.7.2.3 SRS TruBass The SRS(R) TruBassTM audio enhancement technology provides deep, rich bass to small speaker systems without the need for a subwoofer or additional extra physical components. For systems with a subwoofer, TruBassTM complements and enhances bass performance. Psycho-acoustically, when the human ear is presented with a low frequency sound signal that is missing the fundamental harmonic, it will fill in the fundamental frequency based on the higher harmonics that are present. By accentuating the second and higher frequency harmonics of the bass portion of a signal, TruBassTM gives the perception of greatly improved bass response. SRS(R) TruBassTM is implemented on loudspeakers path, headphone path or on both in parallel.
4.8
Smart Volume Control (SVC)
The Smart Volume Control regulates the audio signal level before audio processing. This regulation is necessary in order for the signal level to be independent from the source (terrestrial channels, I2S or SCART), its modulation (FM) and annoying volume changes (advertising, etc.). The Smart Volume Control works as an audio compressor/expander; i.e. when the input signal exceeds the threshold level, a very rapid attenuation (-2 dB/ms) is applied to rescale the signal down to the threshold value. When the input signal is below the threshold level, the previous attenuation is reduced slowly in order to retrieve the original input level (0dB gain). If the input signal is too low, an addition gain of 6 dB can be provided. To personalize the action of the SVC, five parameters are available: 1. Threshold: Maximum quasi-peak level that can be expected on output 2. Peak measurement mode: Select the channel on which the peak measurement must be performed (Left, Right, Center...) 3. Release time: Gain slope applied to the amplification phase 4. Expander switch: To allow a +6dB amplification of small signals in order to reduce the output dynamic range 5. Make up gain: Allows compensation of the signal amplitude limitation thanks to a 0 to 24 dB adjustable gain.
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STV82X8
Dedicated Digital Signal Processor (DSP)
The SVC is implemented on the loudspeakers path, headphone path or on both in parallel (independent settings). Also, the SVC can be applied in six-channel mode (L, R, LS, RS, C and SubW).
4.9
ST Dynamic Bass/ST Bass Enhancer
STV82X8 offers dynamic bass boost processing on the Loudspeakers path: ST Dynamic Bass is a bass boost process that can dramatically increase the bass content of any program without any output level saturation. 3 cutoff frequencies (BASS_FREQ) can be chosen, 100 Hz, 150 Hz and 200 Hz to adapt the effect to your loudspeakers. The amount of bass (BASS_LEVEL) can also be fine tuned in order to adapt the effect loudness.
4.10
5-Band Audio Equalizer
The loudspeakers audio spectrum is split into 5 frequency bands and the gain of each of band can be adjusted within a range from -12 dB to +12 dB in steps of 0.25 dB. The Audio Equalizer may be used to pre-define frequency band enhancement features dedicated to various kinds of music or to attenuate frequency resonances of loudspeakers or the listening environment. The Equalizer is enabled by the LS_EQ_ON bit in the EQ_BT_CTRL register. The gain value for Band X is programmed in register LS_EQ_BANDX. The 5-Band Audio Equalizer is exclusive with Bass-Treble control. Bit LS_EQ_BT_SW in register EQ_BT_CTRL is used to select either the 5-Band Audio Equalizer or the Bass-Treble control for the Loudspeakers path. Depending on the LS Equalizer or LS Bass-Treble value, the volume level can be clamped to the LS output to prevent any possible signal clipping from occuring using the ANTICLIP_LS_VOL_CLAMP bit in the VOLUME_MODES (D7h) register.
Figure 18: Equalizer f1 = 100 Hz, f2 = 316 Hz, f3 = 1 kHz, f4 = 3.16 kHz and f5 = 10 kHz
4.11
Bass/Treble Control
The gain of bass and treble frequency bands for Headphone can be also tuned within a range from -12 dB to +12 dB in steps of 0.25 dB. It may be used to pre-define frequency band enhancement features dedicated to various kinds of music. The Headphone Bass/Treble feature is enabled by setting the HP_BT_ON bit in the EQ_BT_CTRL register. The Bass and Treble gain values are adjusted in registers HP_BASS_GAIN and HP_TREBLE_GAIN, respectively. Depending on the HP Bass-Treble value, the volume level can be clamped to the HP output to prevent any possible signal clipping from occuring using the ANTICLIP_HP_VOL_CLAMP bit in the VOLUME_MODES (D7h) register.
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Dedicated Digital Signal Processor (DSP)
STV82X8
4.12
Automatic Loudness Control
As the human ear does not hear the audio frequency range the same way depending on the power of the audio source, the Loudness Control corrects this effect by sensing the volume level and then boosting bass and treble frequencies proportionally to middle frequencies at lower volume. While maintaining the amplitude of the 1 kHz components at an approximately constant value, the gain values of lower and higher frequencies are automatically progressively amplified up to +18 dB when the audio volume level decreases.The maximum treble amplification can be adjusted from 0 dB (first order loudness) to +18 dB (second order loudness) in steps of 0.125 dB. As the volume is proportional to the external audio amplification power, the loudness amplification threshold is programmable in order to tune the absolute level. The Loudspeakers Loudness function is enabled by setting the LS_LOUD_ON bit in register LS_LOUDNESS. The Loudspeakers Loudness Threshold and Maximum Treble Gain values are also programmed in this register. The Headphone Loudness function is enabled by setting the HP_LOUD_ON bit in register HP_LOUDNESS. The Headphone Loudness Threshold and Maximum Treble Gain values are also programmed in this register. The loudness cut-off frequency is 100 Hz.
4.13
Volume/Balance Control
The STV82X8 provides a Volume/Balance Control for all output channels configuration (except for S/PDIF) with different volume level per channel (L, R, C, LS, RS, SubW, SCART). Its wide range (from +11.875 to -116 dB, in a dB linear scale with a 0.125 dB step) largely covers typical home applications (approx. 60 dB) while maintaining a good S/N ratio.
Figure 19: Volume Control
Output Gain
+11.875 dB
-116 dB Mute 00h IC Control 3FFh
An extra Master Volume Control can apply an extra gain/attenuation on L, R, C, LS, RS and SubW channels. The Volume/Balance Control can operate in one of two different modes:
In Differential mode (default value), the volume control is a common volume value for both the Left and Right Loudspeakers or Headphone channels (see Figure 19) and complimentary balance control is used (see Figure 20).
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STV82X8
Dedicated Digital Signal Processor (DSP)
In Independent mode, the volume for the Left and Right channels for Loudspeakers or Headphone is controlled independently.
Figure 20: Differential Balance
Output Gain
100%
R ig ht C ha nn el C ft Le el nn ha
Mute 200h 000h IC Control (10 bits) 1FFh
4.14
Soft Mute Control
The Digital Soft Mute is applied smoothly (20 ms for 120 dB range) to avoid any switch noise on output. It is available on all output channels pairs:

S/PDIF channel (Left/Right) SCART channels (Left/Right) Loudspeakers channels (Left/Right) Center Subwoofer Headphone/Surround channels (Left/Right)
Another soft mute (analog) is also available on each DAC output.
4.15
Beeper
The beeper is used to generate a tone on the Loudspeakers or/and Headphone outputs. The beeper sound (square wave) is added to the audio signal which is attenuated by 20 dB. The beep sound amplitude includes a smooth attack and decay to avoid any parasitic noise when starting and stopping. It can be used for various applications such as beep sounds for remote control, alarm clock or other features. The Beeper operates in one of two modes:
Pulse mode (beep applications): A tone with a programmable short duration (0.1, 0.25, 0.5 and 1.0 s) is generated. Afterwards, the beeper is automatically disabled and the output is switched back to the audio signal, see Figure 21. Continuous mode (alarm application): A tone with a programmable long duration is generated. Its start and stop controls must be programmed by IC, see Figure 22.
The Beeper function is enabled by setting the BEEPER_ON bit in register BEEPER_ON. Beeper parameters are controlled in register BEEPER_MODE. The beeper tone level and frequency are programmed in register BEEPER_FREQ_VOL. The level (or volume) ranges between 0 dB and -93 dB in steps of 3 dB and the tone frequency ranges between 62.2 Hz and 8 kHz in steps of 1 octave.
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Dedicated Digital Signal Processor (DSP)
STV82X8
A beep generator is shared only by the Loudspeakers or Headphone outputs. Therefore, in the event of simultaneous beeps when in Pulse mode, only the first beep will define the effective duration that will be the same for both outputs.
Figure 21: Pulse Mode
BEEP_ON = 1
BEEP_ON = 0
0.1, 0.25, 0.5 and 1.0 s T predefined
62.5 Hz < f < 8 kHz
Figure 22: Continuous Mode
BEEP_ON = 1 T defined by IC write
BEEP_ON = 0
62.5 Hz < F < 8 kHz
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STV82X8
Analog Audio Matrix (Input / Output)
5
Analog Audio Matrix (Input / Output)
The analog part of the audio matrix can be divided into two parts: the SCART input matrix and the SCART output matrix.
Figure 23: SCART Input Matrix
S1in S2in S3in S4in S5in* MONO_in Select
Audio ADC 2
Digital Matrix
*TQFP100 package only
The SCART input matrix is an input for the digital matrix (after the ADC) which select which source will be sent to the DSP.
Figure 24: SCART1/2/3 Output Matrix
S1in S2in S3in S4in S5in* Stereo DAC MONO_in
2 Soft mute S1out
Select or Mute
*TQFP100 only
The SCART output matrix selects the sound to output, which can be directly a SCART input or the output of the DSP. A mute function is provided to switch off the outputs. A soft-mute function is provided to avoid all spurious sounds when switching from one position to another position. The SCART 2 and 3 output matrices have the same functions as the SCART 1 output matrix. The particularity of the matrix is to accept input signal of 2 VRMS and to have the capability to output such level. In this case, the power supply must be 8 V. The Mono audio input is able to accept signals with a 0.5 VRMS amplitude.
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IS Interface (In / Out)
STV82X8
6
6.1
6.1.1
IS Interface (In / Out)
IS Inputs
IS Inputs in TQFP 80 Package
The STV82X8 can interface with a digital sound decoder. In this case, the digital data can be input at a speed of 0.384 Mbytes/s (3.072 MHz for a 48 kHz sampling frequency with 32 bits of data). A Sample Rate Conversion (SRC) is necessary if input frequency is not 48 kHz (STV82X8 slave) in order to obtain a fixed frequency output from this block (48 kHz).
Note:
The SRC function is only available in single IS input mode. The interface with one IS connection (I2S_DATA0) enables the input of stereo or stereo-coded Dolby(R) Pro Logic(R). One interface with three IS connections connected to the DSP enables the processing of a multichannel signal (maximum of 6 channels).
Figure 25: TQFP 80 IS Input Block Diagram
I2S_DATA0 fS Input = 32 to 48 kHz I2S_DATA1 fS Input = 48 kHz only I2S_DATA2 fS Input = 48 kHz only I2S_SCLK fS Input * 64 I2S_LR_CLK fS Input = 32 to 48 kHz
Audio Processing
48 kHz DSP
Processing
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STV82X8 6.1.2 IS Inputs in TQFP 100 Package
IS Interface (In / Out)
An additional (auxiliary) asynchronous input is available in the TQFP100 package. An I2SD_DATA input for external delay is also available, but it must be in phase with the IS output clocks.
Figure 26: TQFP100 IS Input Block Diagram
I2S_DATA0 fS Input = 32 to 48 kHz I2S_DATA1 fS Input = 48 kHz only I2S_DATA2 fS Input = 48 kHz only I2S_SCLK fS Input * 64 I2S_LR_CLK fS Input = 32 to 48 kHz I2SA_DATA fS Input = 32 to 48 kHz I2SA_SCLK fS Input * 64 I2SA_LR_CLK fS Input = 32 to 48 kHz I2SD_DATA fS Input = 48 kHz in phase with I2SO_LR_CLK and I2SO_SCLK Audio Processing
48 kHz DSP
Processing
6.2
6.2.1
IS Outputs
IS Outputs in TQFP 80 Package
A digital stereo output (IS compatible) is also available for routing the demodulated signal or a converted input audio signal to an external device. In this case, the I2S_DATA0 signal and all clock signals are set as outputs by setting bit D5 in register RESET to 1 (and bit D6 for the clocking). The STV82X8 drives the serial bus (I2S_SCLK, I2S_LR_CLK, and I2S_DATA0) in master mode in 64.fs format with a sampling frequency (fs) of 48 kHz. The I2S_PCM_CLK signal can be used as a master clock for the slave interface, if required. Both standard and non-standard modes are available.
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IS Interface (In / Out)
.
Figure 27: TQFP 80 IS Output Block Diagram
STV82X8
I2S_DATA0 fS Output = 48 kHz I2S_SCLK fS Output * 64 I2S_LR_CLK fS Output = 48 kHz I2S_PCM_CLK
Audio Processing
48 kHz DSP
Processing
6.2.2
IS Outputs in TQFP 100 Package
Two digital stereo outputs (IS compatible) are available for routing the demodulated signal or a converted input audio signal to an external device or perform an external delay. In this case, the I2SO_DATA0 and I2SO_DATA1 signals are available with all IS inputs active. The STV82X8 drives the serial bus (I2SO_SCLK,I2SO_LR_CLK, I2SO_DATA0, and I2SO_DATA1) in master mode in 64.fs format with a sampling frequency (fs) of 48 kHz. The I2S_PCM_CLK signal can be used as a master clock if required for the slave interface. Both standard and non-standard modes are available. .
Figure 28: TQFP100 IS Output Block Diagram
I2SO_DATA0 fS Output = 48 kHz I2SO_DATA1 fS Output = 48 kHz
Audio Processing
I2SO_SCLK fS Output * 64 I2SO_LR_CLK fS Output = 48 kHz I2S_PCM_CLK
48 kHz DSP
Processing
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STV82X8
Note:
IS Interface (In / Out)
The Input and Output modes for IS are exclusive in the TQFP80 package.
Figure 29: IS Data Format: Lch = LOW, Rch = HIGH (IS Input or Output mode)
1/fs Lch
I2S_LR_CLK
Rch
I2S_SCLK (= 64fs)
I2S_DATAx (standard mode)
1
2
3
22
23
24
1
2
3
22
23
24
1
2
MSB I2S_DATAx (non-standard mode) 1 2 3 22 23 24
LSB 1 2
MSB 3 22 23 24
LSB 1 2 3
MSB
LSB
MSB
LSB
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S/PDIF Input/Output
STV82X8
7
S/PDIF Input/Output
An S/PDIF output is available for connection with an external decoder/amplifier. An internal multiplexer allows selection of either the internal signal or the external signal connected on the S/ PDIF input (for example, the signal provided by the external MPEG audio / Dolby Digital decoder). The outputted internal signal can be selected from:

L/R C/Sub HP or Surround SCART
A Mute facility is also provided on the S/PDIF output.
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STV82X8
Power Supply Management
8
Power Supply Management
A mixed supply voltage environment requires the following voltages:

3.3V capable inputs/outputs for digital pins; 1.8V digital core; 8V capable inputs/outputs for analog audio interfaces (capability to output 2 VRMS for SCART requirements); 3.3V for stereo ADC and DAC (analog part); 1.8V for stereo ADC and DAC (digital part); 1.8V for IF ADC and AGC.

These voltages will be delivered by the application with an accuracy of 5%. For more information, refer to Section 16.3: Power Supply Data. Other specific DC voltages or features are provided:

Voltage Reference and Biasing Generation (AGC, ADCs, DACs), Bandgap reference.
8.1
Standby Mode (Loop-through mode)
The STV82X8 provides a Loop-through mode configuration that bypasses IC functions via a SCART I/O pin (Full Analog Path only). In this case, only a minimum power of 200 mW is required. In Standby mode, the digital and analog power supplies are switched off, except for pins VCC_H, VCC33_LS, VCC33_SC, and VCC_NISO which are used to maintain the SCART path with the last configuration programmed by analog matrixing (register SCART1_2_OUTPUT_CTRL and SCART3_OUTPUT_CTRL). When switching back to normal Full Power mode, all IC registers are reset except for those used in Standby mode to maintain the original configuration. In Standby mode, the IC bus does not operate. However, the bus can still be used by other ICs since the IC I/O pins (SDA and SCL) of the STV82X8 are forced into a high-impedance configuration.
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Additional Controls and Flags
STV82X8
9
Additional Controls and Flags
This logic contains:

the headphone detection, the IRQ generation, signal to be output to the MCU, the IC bus expander output pin.
9.1
Headphone Detection
For headphone, the HP_DET input can be used to automatically mute the Loudspeakers and Subwoofer outputs when the HP_LS_MUTE bit is set in register HEADPHONE_CONFIG (active low). When a headphone is detected (the HP_DET pin is set to 0) and the Mute function is enabled. Each change on the HP_DET pin generates an IRQ request to the microprocessor on the IRQ pin.
9.2
IRQ Generation
Four IRQs are generated by the STV82X8. On each IRQ generation, the IRQ pin is set to 1. The pending IRQ status must be read at the IS address 81h and the acknowledge is done by writing 0 to this register. The four availables IRQs are: IRQ0: The identified TV sound standard is displayed in register AUTOSTD_STATUS. Each change in the detected standard is flagged to the host system via hardware pin IRQ. The flag must be reset by re-programming the IRQ bit in register AUTOSTD_CTRL and then checking the detected standard status by reading registers AUTOSTD_DEM_STATUS and AUTOSTD_TIME. IRQ1: This IRQ is enabled only in digital input mode. In case of IS synchronisation loss, this IRQ is set to 1. IRQ2: This IRQ is set to 1 when the device detects any change on the HP Detection pin (Headphone connection or deconnection). IRQ3: On the STV82X8, same pins are used for both Headphone and Surround loudspeaker signal output. A change in the Headphone configuration (HP active or not active) will lead to a signal switch on those hardware pins. In order to ensure a smooth audio transition, the output is soft muted before the signal is switched. The IRQ3 is then set to 1 to advise the master processor that the signal has been switched and to request a HP/Srnd Ouput Un-Mute.
9.3
IC Bus Expander
Pin BUS_EXP can be used to control external switchable IF SAW filters or audio switches. This pin can be directly programmed by register RESET.
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STV82X8
STV82X8 Reset
10
STV82X8 Reset
All STV82X8 features are controlled via the IC bus. The STV82X8 can be "reset" in 2 ways: 1. By Software via the IC bus: This clears all synchronous logic, except for the IC bus registers. 2. By Hardware via the RESET pin: In addition to clearing all synchronous logic, the RESET input (active on the low level) resets all the IC bus registers to the default values listed below.
Table 5: RESET Default Values Function
Demodulation Auto-standard Scanned Standards Audio Outputs Automatic Mute Mode Loudspeaker Source Loudspeaker Volume Loudspeaker L/R Balance Subwoofer Headphone Source Headphone Automatic Detection Headphone Volume Headphone L/R Balance SCART1 Output SCART2 Output SCART3 Output IS Output (TQFP 100) ON Demodulated Sound -40 dB, Differential Mode, Muted L/R = 100% -40 dB / OFF Demodulated Sound ON -40 dB, Differential Mode, Muted L/R = 100% Demodulated Sound SCART1 Source SCART2 Source Mute OFF M/N BTSC
Default Mode
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IC Interface
STV82X8
11
11.1
IC Interface
IC Address and Protocol
The STV82X8 IC interface works in Slave mode and is fully compliant with IC standards in Fast mode (maximum frequency of 400 kHz). Two pairs of IC chip addresses are used to connect two STV82X8 chips to the same IC serial bus. The device address pairs are defined by the polarity of the ADR_SEL pin and are listed in the following table:
Table 6: IC Read/Write Addresses ADR
LOW (connected to GND1) HIGH (connected to VDD1)
Write Address (W)
80h 84h
Read Address (R)
81h 85h
Protocol Description
Write Protocol
Start WA Sub-address A Data A .... A Data A Stop
Read Protocol
Start WA Sub-address A Stop Start R A Data A .... A Data N

W = Write address, R = Read address, A = Acknowledge, N = No acknowledge. Sub-address is the register address pointer; this value auto-increments for both write and read.
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STV82X8
IC Interface
11.2
Start-up and Configuration Change Procedure
Figure 30: Flowchart
Power ON
Hardware Reset (by pin 43)
NOTE: This HW reset after Power ON is mandatory to prevent incorrect device configuration.
Clock PLLs progammation
(for oscillator values other than 27 MHz)
(Registers FS1 and FS2)
Load Patch File
(By IC transfer)
HW_RESET bit = 1 (bit 2 in HOST_CMD register)
(DSP RUN)
INIT_MEM bit ? (bit 0 in DSP_STATUS register)
=0
(DSP inititialization)
=1
Device Configuration Set-up
(Analog or Digital)
HOST_RUN bit = 1 (bit 0 in DSP_RUN register)
(Start DSP processing)
INIT_MEM bit = 0
(Change configuration)
HOST_NO_INIT bit = 1 (bit 1 in DSP_RUN register)
(OPTIONAL)
(Registers 85h to FFh are not reset)
HOST_RUN bit = 0
(Stop DSP processing)
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Register List
STV82X8
12
Note:
Register List
The unused bits (defined as `Reserved') in the IC registers must be kept to zero. The system clock registers (from address 08h to 0Bh and from address 5Ah to 5Dh) do not need to be modified if a standard 27 MHz crystal oscillator is used. The default values of the demodulator registers (from address 0Ch to 55h) are for optimum performances and any change is not recommended, except for:

CAROFFSET1 (22h) to compensate IF carrier frequency with an out-of-standard offset. Soundlevel Prescaling PRESCALE_DEMOD_MONO (94h), PRESCALE_DEMOD_STEREO (95h), PRESCALE_DEMOD_SAP (96h), PRESCALE_SCART (97h), PRESCALE_I2S0 (98H), PRESCALE_I2S1 (99H), PRESCALE_I2S2 (9AH) to equalize demodulated or external audio signal before audio processing. Peak detector registers PEAK_DETECTOR (9Bh), PEAK_L (9Ch), PEAK_R (9Dh), PEAK_L_R (9Eh) can be used to measure internal sound level.
Sound source selection for each audio output channel to be done using AUDIO_MATRIX1 (A2h), AUDIO_MATRIX2 (A3h) and AUDIO_MATRIX3 (A4h). Register AUTOSTD_CTRL (8Ah) is used to select the list of mono, stereo and SAP signals to be recognized automatically. Note: () used in reset value column means that the bit or the byte is read-only. (S) symbol indicates that the field value is represented in signed binary format.
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STV82X8
Register List
12.1
IC Register Map
By default, all IC registers controlled by Automatic Standard Recognition System (Autostandard) are forced to Read-only mode for the user. These registers and bits are shaded in Table 1.
Table 7: List of IC Registers (Sheet 1 of 2) Name Ad. Reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
IC General Control
CUT_ID RESET 00h 01h (0000 0001) 0000 0000 0 BUS_EXP 0
I2S_CO_EN I2S_DO_EN
CUT_NUMBER[5:0] EN_STBY CLOCK_ DOWN 0 LOCK_ MODE 0 SOFT_ LRST1 SOFT_RST
I2S_CTRL I2S_STAT I2S_SYNC_OFFSET
04h 05h 06h
0000 0001 (0000 0000) (0000 0000)
I2S_PLL 0
SYNC_ SIGN 0
I2S_SRC 0
LOCK_TH[1:0] 0 0
SYNC_CST[1:0] LR_OFF LOCK_ FLAG
I2S_SFO[7:0]
Clocking 1
SYS_CONFIG FS1_DIV FS1_MD FS1_PE_H FS1_PE_L 07h 08h 09h 0Ah 0Bh 0000 1010 0001 0011 0001 0001 0011 0110 0000 0000 SYNC_PLL EN_PROG 0 OPEN_PLL 0 0 0 PE_H1[7:0] PE_L1[7:0] INPUT_FREQ[3:0] NDIV1[1:0] 0 MD1[4:0] BIT[1:0] SDIV1[2:0]
Demodulator
DEMOD_CTRL DEMOD_STAT AGC_CTRL AGC_GAIN DC_ERR_IF 0Ch 0Dh 0Eh 0Fh 10h 0000 0001 (0000 0000) 0001 0001 (0000 0000) (0000 0000) 0 0 0 0 0 0 0 0 0
IF_SELECT
0 0
0 0 AGC_REF[2:0] 0
DEMOD_MODE[2:0] FM1_CAR FM1_SQ
AGC_CST[1:0] SIG_OVER SIG_ UNDER
AGC_ERR[4:0] DC_ERR[7:0]
Demodulator Channel 1
CARFQ1H CARFQ1M CARFQ1L FIR1C0 FIR1C1 FIR1C2 FIR1C3 FIR1C4 FIR1C5 FIR1C6 FIR1C7 ACOEFF1 BCOEFF1 CRF1 CETH1 SQTH1 CAROFFSET1 CHANNEL_GAIN 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 0010 1110 1110 0000 0000 0000 0000 0001 0000 0000 1111 1110 1111 1100 0000 0000 0000 1011 0001 1001 0010 0100 0010 0010 0000 1001 (0000 0000) 0010 0000 0011 1100 0000 0000 0000 0010 0 0 0 CARFQ1[23:16] CARFQ1[15:8] CARFQ1[7:0] FIR1C0[7:0] (S) FIR1C1[7:0] (S) FIR1C2[7:0] (S) FIR1C3[7:0] (S) FIR1C4[7:0] (S) FIR1C5[7:0] (S) FIR1C6[7:0]6 (S) FIR1C7[7:0] (S) ACOEFF1[7:0] BCOEFF1[7:0] CRF1[7:0] (S) CETH1[7:0] SQTH1[7:0] CAROFFSET1[7:0] (S) 0 0 0 CH_GAIN[1:0]
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Register List
Table 7: List of IC Registers (Sheet 2 of 2) Name
BTSC Stereo and SAP
STEREO_CONF STEREO_FSM_CONF STEREO_LEVEL_H STEREO_LEVEL_L SAP_CONF SAP_LEVEL_H SAP_LEVEL_L STE_CAR_LEVEL STE_PLL_STATUS STEREO_SAP_STATUS PLL_P_GAIN PLL_I_GAIN SAP_SQ_TH 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 00111000 00001110 00100000 00010000 00000000 00100000 00010000 (00000000) (00000000) (00000000) 01101100 0000011 00110000 0 0 0 0 0 0 OVER 0 0 0 0 LOCK_TH_STE[7:4] 0 BYPASS FSM_OFF STE_LEV_H[7:0] STE_LEV_L[7:0] 0 0 0 0 LOOP_GAIN[1:0] GAIN_INI[2:0]
STV82X8
Ad.
Reset
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FREQ_PIL
RESET STE_DEM
SAP_SEL
SAP_LEV_H[7:0] SAP_LEV_L[7:0] STE_CAR_LEV[7:0] LOOP_GAIN[3:0] LOCK_DET STE_DET 0 OVER 0 LOCK_DET SQ_DET STE_DET SAP_DET
PLL_P_GAIN[7:0] 0 SAP_SQ_TH[7:0] PLL_I_GAIN[3:0]
Analog and I2S Out Control
I2S_ADC_CTRL SCART1_2_OUTPUT_CTRL SCART3_OUTPUT_CTRL I2SO_DATA_CTRL 56h 57h 58h 59h 0000 1000 1010 1000 0000 1011 0000 0000 I2S_DATA0_CTRL
SC2_MUTE
0
ADC_ POWER_UP SC1_MUTE
ADC_INPUT_SEL[2:0] SC1_OUTPUT_SEL[2:0] SC3_OUTPUT_SEL[2:0] I2SO_DATA0_CTRL
SC2_OUTPUT_SEL[2:0] 0 0 I2SO_DATA1_CTRL 0
0 0
SC3_MUTE
0
Clocking 2
FS2_DIV FS2_MD FS2_PE_H FS2_PE_L 5Ah 5Bh 5Ch 5Dh 0001 0001 0001 0001 0101 1100 0010 1001 0 0 0 NDIV2[1:0] 0 PE_H2[7:0] PE_L2[7:0] 0 MD2[4:0] SDIV2[2:0]
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STV82X8
Register List
12.2
Software Registers
Table 8: List of IC Registers (Sheet 1 of 5) Name Addr. Reset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
DSP Control
HOST_CMD 80h 0000 0000 IT_IN_DSP 0 0 IRQ5 (HP/Srnd unmute ready) 0 0 IRQ3 (I2S SRC input freq change) PATCH_WR HW_RESET ITE_ENABL EMUL_SW E IRQ2 (I2S sync found) IRQ1 (I2S sync lost) IRQ0 (AutoStanda rd)
IRQ_STATUS
81h
0000 0000
IRQ7
IRQ6
IRQ4 (HP detected)
FW_VERSION ONCHIP_ALGO DSP_STATUS DSP_RUN I2S_IN_CONFIG I2S_IN_SHIFT_RIGHT I2S_IN_MASK
82h 83h 84h 85h 86h 87h 88h
(0000 0001) (0000 0000) 0000 0000 0000 0000 1000 1110 0000 1000 0001 1111 0 0 0 LOCK_ MODE_EN 0 0 0 0 TEST_MOD E_INPUT RESET_I2S 0 0
SOFT_VERSION[7:0] PROLOGIC MULTI_I2S_ _TYPE IN 0 0 TRUBASS 0 TRUSURR OUND 0 PROLOGIC 0 MULTICHA NNEL_OUT INIT_MEM
TEST_MODE 0 0 0
INPUT_CONFIG
REGISTER HOST_RUN S_RESET DATA_CFG I2S_MODE
LRCLK_STA LRCLK_PO SCLK_POL RT LARITY ARITY
SHIFT_RIGHT_RANGE WORD_MASK
I2S_IN_STATUS
89h
1000 0(000)
ENABLE_IR ENABLE_IR ENABLE_IR AUTO_SRC Q_SRC_FR Q_SYNC_F Q_SYNC_L _SYNC EQ_CHANG OUND OST E
0
I2S_INPUT_FREQ
Automatic Standard Detection
AUTOSTD_CTRL AUTOSTD_TIME AUTOSTD_STATUS AUTOSTD_DEM_STATU S DMA_FORCE_OFF I2S_IN_DELAY_CONFIG 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 0000 0000 0000 1010 (0000 0000) (0000 0000) 0000 0000 0000 0111 MONO_SA SIHGLESH FORCE_SQ FORCE_SQ AUTO_MUT SAP_CHEC STEREO_C MONO_CH P_MATRIX_ OT _SAP _MONO E K HECK ECK CTRL 0 0 0 0 0 0 0 OVERFLO W 0 0 0 0 LCK_DET 0 SYNC 0 ST_DET ADC STEREO_TIME SAP_OK SAP_SQ I2S2 STEREO_ OK SAP_DET I2S1 FM_TIME MONO_OK FM1_CAR I2S0 DATA_CFG AUTOSTD_ ON FM1_SQ DEMOD I2S_MODE
LRCLK_STA LRCLK_PO SCLK_POL RT LARITY ARITY
Demodulator
BTSC_FINE_PRESCALE _ST BTSC_FINE_PRESCALE _SAP BTSC_CONTROL 90h 91h 0000 0000 0000 0000 FINE_PRES CAL_SELE CT_SAP 0 BTSC_FINE_PRESCALE_ST[7:0] (S) BTSC_FINE_PRESCALE_SAP[7:0] (S)
92h
0010 0000
DBX_DEMATRIX
DBX_ON
DEEMPHASIS_CH1
DEEMPHASIS_CH0
DCREMOVAL
93h
0011 0111
0
DEEMPHAS DBX_FILTE IS_FILTER_ R_SELECT SELECT
0
DC_DEMO DC_DEMO DC_SCART D_POST_O D_PRE_ON _ON N
Audio Preprocessing & Selection
PRESCALE_DEMOD_M ONO PRESCALE_DEMOD_ST EREO PRESCALE_DEMOD_SA P PRESCALE_SCART 94h 0000 0000 PRESCALE _DEMOD_S ELECT_SA P 0 0 0 PRESCALE_DEMOD_MONO[6:0] (S)
95h 96h 97h
0000 0000 0000 0000 0000 0000
PRESCALE_DEMOD_STEREO[6:0] (S) PRESCALE_DEMOD_SAP[6:0] (S) PRESCALE_SCART[6:0] (S)
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Register List
Table 8: List of IC Registers (Sheet 2 of 5) Name
PRESCALE_I2S0 PRESCALE_I2S1 PRESCALE_I2S2 PEAK_DETECTOR PEAK_L PEAK_R PEAK_L_R
STV82X8
Addr.
98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh
Reset
0000 0000 0000 0000 0000 0000 0000 0000 0(000 0000) 0(000 0000) 0(000 0000)
Bit 7
0 0 0 0 OVERLOAD _L OVERLOAD _R OVERLOAD _L_R
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PRESCALE_I2S0[6:0] (S) PRESCALE_I2S1[6:0] (S) PRESCALE_I2S2[6:0] (S) PEAK_L_R_RANGE[2:0] PEAK_DET_INPUT[2:0] PEAK_L[6:0] PEAK_R[6:0] PEAK_L_R[6:0 PEAK_DET ECTOR_ON
Matrixing
DOWNMIX_MODE DOWNMIX_DUAL_MOD E DOWNMIX_CONFIG AUDIO_MATRIX1 AUDIO_MATRIX2 AUDIO_MATRIX3 CHANNEL_MATRIX_LS 9Fh A0h A1h A2h A3h A4h A5h 0111 1111 0000 0000 0000 0001 0001 0010 0000 0010 0001 0000 0000 0010 LTRT_OUT_ MODE 0 0 0 0 0 0 0 0 0 0 0 MIX_OUT_MODE[2:0] 0 DUAL_ON LFE_IN MIX_IN_MODE[2:0] LTRT_DUAL_SELECT [1:0] LR_UPMIX LS_OUT[2:0] SCART1_OUT[2:0] DELAY_OUT[2:0] 0 CM_MATRIX_LS[2:0] NORMALIZ E
LS_DUAL_SELECT[1:0] CENTER_FACTOR[1:0]
SRND_FACTOR[1:0] HP_OUT[2:0]
SCART2_OUT[2:0] SPDIF_OUT[2:0] 0
AUTOSTD_ AUTOSTD_ CONTROL_ CONTROL_ LS SPDIF AUTOSTD_ CONTROL_ HP AUTOSTD_ CONTROL_ SCART1 AUTOSTD_ CONTROL_ SCART2
CHANNEL_MATRIX_HP
A6h
0000 0000
CM_SOURCE_HP[2:0]
CM_POSTION_HP[2:0]
CM_MATRIX_HP[2:0]
CHANNEL_MATRIX_SC ART1 CHANNEL_MATRIX_SC ART2 CHANNEL_MATRIX_SP DIF DEMOD_DC_LEVEL
A7h
0000 0000
CM_SOURCE_SCART1[ 2:0] CM_SOURCE_SCART2[ 2:0]
CM_POSTION_SCART1[ 2:0] CM_POSTION_SCART2[ 2:0] CM_POSTION_SPDIF[ 2:0] DEMOD_DC_LEVEL[7:0] (S)
CM_MATRIX_SCART1[2:0]
A8h
0000 0000
CM_MATRIX_SCART2[2:0]
A9h AAh ABh ACh
0000 0000 (0000 0000) 0000 0000 0000 0000 0 0
CM_SOURCE_SPDIF[3:0]
CM_MATRIX_SPDIF[2:0]
0 0
0 0
0 0
0 0
0 0
0 0
0 0
Audio Processing
AV_DELAY_CONFIG AV_DELAY_TIME_LS AV_DELAY_TIME_HP PROLOGIC2_CONTROL PROLOGIC2_CONFIG PROLOGIC2_DIMENSIO N PROLOGIC2_LEVEL NOISE_GENERATOR PCM_SRND_DELAY PCM_CENTER_DELAY ADh AEh AFh B0h B1h B2h B3h B4h B5h B6h 0000 0000 0000 0000 0000 0000 0111 0110 0000 0000 0000 0000 0000 0011 0000 0000 0000 0000 0000 0000 10_DB_ATT ENUATE 0 0 SRIGHT_ NOISE 0 0 SLEFT_ NOISE 0 0 0 PL2_LFE 0 0 0 0 0 0 0 0 DOLBY_DE AV_DELAY_ LAY_ON ON
AV_DELAY_TIME_LS[7:0] AV_DELAY_TIME_HP[7:0] PL2_OUTPUT_DOWNMIX[2:0] 0 0 PL2_MODES[2:0] PL2_RS_P OLARITY PL2_PANO RAMA PL2_ACTIV E PL2_AUTO BALANCE
PL2_SRND_FILTER[1:0] 0 PL2_LEVEL[7:0] SUB_ NOISE CENTER_ NOISE
PL2_C_WIDTH[2:0]
PL2_DIMENSION[2:0]
RIGHT_ NOISE
LEFT_ NOISE
NOISE_ON
DOLBY_DELAY_SRND[4:0] DOLBY_DELAY_CENTER[3:0]
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STV82X8
Table 8: List of IC Registers (Sheet 3 of 5) Name
TRUSRND_CONTROL TRUSRND_DC_ELEVATI ON TRUSRND_INPUT_GAIN TRUBASS_LS_CONTRO L TRUBASS_LS_LEVEL TRUBASS_HP_CONTRO L TRUBASS_HP_LEVEL SVC_LS_CONTROL SVC_LS_TIME_TH SVC_LS_GAIN SVC_HP_CONTROL SVC_HP_TIME_TH SVC_HP_GAIN WIDESRND_CONTROL WIDESRND_FREQ WIDESRND_LEVEL OMNISRND_CONTROL DYNAMIC_BASS_LS DYNAMIC_BASS_HP
Register List
Addr.
B7h B8h B9h BAh BBh BCh BDh BEh BFh C0h C1h C2h C3h C4h C5h C6h C7h C8h C9h
Reset
0000 1000 0000 1100 0000 0000 0000 0110 00001 1001 0000 0110 0000 1001 0000 0010 0000 0000 0000 1111 0000 0010 0000 0000 0000 1111 0000 0100 0001 0101 1000 0000 0000 1100 0110 0010 0110 0010
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DIALOG_CL HEADPHO ARITY_ON NE_ON
TRUSRND_INPUT_MODE[3:0] TRUSRND_DC_ELEVATION[7:0] TRUSRND_INPUT_GAIN[7:0]
TRUSRND_ TRUSRND_ BYPASS ON
0
0
0
0
TRUBASS_LS_SIZE[2:0]
TRUBASS_ LS_ON
TRUBASS_LS_LEVEL[7:0] SRS_TSXT _GAIN_ON 0 0 0 TRUBASS_HP_SIZE[2:0] TRUBASS_ HP_ON
TRUBASS_HP_LEVEL[7:0] 0 0 SVC_LS_TIME[2:0] 0 0 0 0 SVC_HP_TIME[2:0] 0 0 0 0 0 0 0 0 0 0 0 0 SVC_LS_INPUT[1:0] SVC_ LS_AMP SVC_ LS_ON
SVC_LS_THRESHOLD[4:0] SVC_LS_MAKE_UP_GAIN[5:0] 0 0 SVC_ LHP_AMP SVC_ HP_ON
SVC_HP_THRESHOLD[4:0] SVC_HP_MAKE_UP_GAIN[5:0] 0 WIDESRND WIDESRND WIDESRND _STEREO _MODE _ON WIDESRND_TREBLE[ 1:0]
WIDESRND_BASS[1:0]
WIDESRND_MEDIUM[ 1:0]
WIDESRND_GAIN[7:0] ST_VOICE[1:0] SRND_PHA SE_INV LS_BASS_LEVEL[4:0] HP_BASS_LEVEL[4:0] LS_BASS_ ENHANCE_ HP_FILTER 0 0 OMNISRND_INPUT_MODE[3:0] LS_BASS_FREQ[1:0] HP_BASS_FREQ[1:0] OMNISRND _ON LS_DYN_B ASS_ON HP_DYN_B ASS_ON
BASS_ENHANCE_LS
CAh CBh
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1000 0000 0000 0100 0000 0100
0 0 0
0 0 0
LS_BASS_ENHANCE_SCALE[2:0] 0 0 0 0 0 HP_BT_ON
LS_BASS_ LS_BASS_ ENHANCE_ ENHANCE_ CUTOFF ON 0 LS_EQ_BT _SW 0 LS_EQ_ON
EQ_BT_CONTROL LS_EQ_BAND1 LS_EQ_BAND2 LS_EQ_BAND3 LS_EQ_BAND4 LS_EQ_BAND5 LS_BASS_GAIN LS_TREBLE_GAIN HP_BASS_GAIN HP_TREBLE_GAIN OUTPUT_BASS_MNGT LS_LOUDNESS HP_LOUDNESS
CCh CDh CEh CFh D0h D1h D2h D3h D4h D5h D6h D7h D8h
EQ_BAND1[7:0] (S) EQ_BAND2[7:0] (S) EQ_BAND3[7:0] (S) EQ_BAND4[7:0] (S) EQ_BAND5[7:0] (S) LS_BASS[7:0] (S) LS_TREBLE[7:0] (S) HP_BASS[7:0] (S) HP_TREBLE[7:0] (S) BASS_MAN ST_LFE_AD DOLBY_PR AGE_ON D OLOGIC 0 0 SUB_ ACTIVE GAIN_ SWITCH OCFG_NUM[2:0] LS_ LOUD_ON HP_ LOUD_ON
LS_LOUD_THRESHOLD[2:0] HP_LOUD_THRESHOLD[2:0]
LS_LOUD_GAIN_HR[2:0] HP_LOUD_GAIN_HR[2:0]
Volume
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Register List
Table 8: List of IC Registers (Sheet 4 of 5) Name
VOLUME_MODES LS_L_VOLUME_MSB LS_L_VOLUME_LSB LS_R_VOLUME_MSB LS_R_VOLUME_LSB LS_C_VOLUME_MSB LS_C_VOLUME_LSB LS_SUB_VOLUME_MSB LS_SUB_VOLUME_LSB LS_SL_VOLUME_MSB LS_SL_VOLUME_LSB LS_SR_VOLUME_MSB LS_SR_VOLUME_LSB LS_MASTER_VOLUME_ MSB LS_MASTER_VOLUME_ LSB HP_L_VOLUME_MSB HP_L_VOLUME_LSB HP_R_VOLUME_MSB HP_R_VOLUME_LSB AUX_VOLUME_INDEX AUX_L_VOLUME_MSB AUX_L_VOLUME_LSB AUX_R_VOLUME_MSB AUX_R_VOLUME_LSB
STV82X8
Addr.
D9h DAh DBh DCh DDh DEh DFh E0h E1h E2h E3h E4h E5h E6h E7h E8h E9h EAh EBh ECh EDh EEh EFh F0h
Reset
1101 1111 1001 1000 0000 0000 0000 0000 0000 0000 1001 1000 0000 0000 1001 1000 0000 0000 1001 1000 0000 0000 0000 0000 0000 0000 1110 1000 0000 0000 1001 1000 0000 0000 0000 0000 0000 0000 0000 0001 1101 1101 0000 0000 0000 0000 0000 0000
Bit 7
Bit 6
Bit 5
0
Bit 4
SCART2_ VOLUME_ MODE
Bit 3
SCART1_ VOLUME_ MODE
Bit 2
HP_ VOLUME_ MODE
Bit 1
SRND_ VOLUME_ MODE
Bit 0
LS_ VOLUME_ MODE
ANTCLIP_H ANTICLIP_L P_VOL_CL S_VOL_CL AMP AMP
LS_L_VOLUME_MSB[7:0] 0 0 0 0 0 0 LS_L_VOLUME_LSB[1:0]
LS_R_VOLUME_MSB[7:0] 0 0 0 0 0 0 LS_R_VOLUME_LSB[1:0]
LS_C_VOLUME_MSB[7:0] 0 0 0 0 0 0 LS_C_VOLUME_LSB[1:0]
LS_SUB_VOLUME_MSB[7:0] 0 0 0 0 0 0 LS_SUB_VOLUME_LSB[ 1:0]
LS_SL_VOLUME_MSB[7:0] 0 0 0 0 0 0 LS_SL_VOLUME_LSB[ 1:0]
LS_SR_VOLUME_MSB[7:0] 0 0 0 0 0 0 LS_SR_VOLUME_LSB[ 1:0]
LS_MASTER_VOLUME_MSB[7:0] 0 0 0 0 0 0 LS_MASTER_VOLUME_ LSB[1:0]
HP_L_VOLUME_MSB[7:0] 0 0 0 0 0 0 HP_L_VOLUME_LSB[1:0]
HP_R_VOLUME_MSB[7:0] 0 0 0 0 0 0 0 0 0 0 0 0 HP_R_VOLUME_LSB [1:0] AUX_VOLUME_SELECT [1:0]
AUX_L_VOLUME_MSB[7:0] 0 0 0 0 0 0 AUX_L_VOLUME_LSB[ 1:0]
AUX_R_VOLUME_MSB[7:0] 0 0 0 0 0 0 AUX_R_VOLUME_LSB[ 1:0]
Mute
MUTE_SOFTWARE F1h 1111 1111 HP D_MUTE SPDIF_D_M UTE SCART2_ D_MUTE SCART1_D SRND_D_M _MUTE UTE SUB_ D_MUTE C_ D_MUTE LS_ D_MUTE
Beeper
BEEPER_ON F2h 0000 0000 0 0 0 0 0 BEEPER_SOUND_SELE CT[1:0] BEEPER_ ON
BEEPER_MODE BEEPER_FREQ_VOL
F3h F4h
0100 0011 0111 0110
BEEPER_DECAY[1:0] BEEPER_FREQ[2:0]
BEEPER_ BEEPER_DURATION[1:0] CONTINUO US
BEEPER_PATH[1:0]
BEEPER_VOLUME[4:0]
SPDIF Out Configuration
SPDIF_OUT_CHANNEL_ STATUS F5h 0000 0010 0 0 0 0 0 SPDIF_CO SPDIF_CO SPDIF_NO_ NSUMER_P PYRIGHT PCM RO
Headphone Configuration
HP_SCART2_CONFIG F6h 0000 0010 0 KARAOKE_ MIX SCART2_OUT_SELECT HP_FORCE HP_LS_ MUTE HP_DET_ ACTIVE HP_ DETECTED
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STV82X8
Table 8: List of IC Registers (Sheet 5 of 5) Name
DAC Control
DAC_CONTROL DAC_SW_CHANNELS SPDIF_SW_CHANNELS F7h F8h F9h 0001 1111 0000 0000 0000 0000 0 0 SPDIF_ MUX
Register List
Addr.
Reset
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DAC_SCAR DAC_SHP_ DAC_CSUB DAC_LSLR T_MUTE MUTE _MUTE _MUTE SCART_SW[1:0] DELAY_SW[1:0]
POWER_ UP
C_SUB_SW[1:0] 0 0
SUR_HP_SW[1:0] 0 0
SPDIF_SW[1:0] L_R_SW[1:0]
AutoStandard Coefficients Settings
AUTOSTD_FSM AUTOSTD_COEFF_CTR L AUTOSTD_COEFF_IND EX_MSB AUTOSTD_COEFF_IND EX_LSB AUTOSTD_COEFF_VAL UE PATCH_VERSION FAh FBh 0000 0000 0000 0001 0 0 0 0 0 0 0 0 0 FSM_STATE 0 AUTOSTD_COEFF_ CTRL[1:0] 0 AUTOSTD_ COEFF_IN DEX_MSB
FCh
0000 0000
0
0
0
0
0
0
FDh FEh FFh
0000 0000 0000 0000 0000 0000
AUTOSTD_COEFF_INDEX_LSB[7:0] AUTOSTD_COEFF_VALUE[7:0] PATCH_VERSION[7:0]
12.3
STV82X8 General Control Registers
CUT_ID Version Identification
Address: 00h Type: R Bit 7 0 Bit 6 0 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CUT_NUMBER[5:0]
Bit Name
Bits[7:6] CUT_NUMBER[5:0]
Reset
00 Reserved
Function
000001 Dice Version Identification
RESET
Address: 01h Type: R/W Bit 7 BUS_EXP Bit 6 I2S_CO_EN Bit 5 I2S_DO_EN
Software Reset Register
Bit 4 EN_STBY
Bit 3 CLOCK_DOW N
Bit 2 0
Bit 1 SOFT_LRST1
Bit 0 SOFT_RST
Description The built-in Automatic Standard Recognition System (Autostandard) can be disabled. In this case, the Software Reset function (bits SOFT_LRST1 and SOFT_LRST2) can be used to implement the
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Register List
STV82X8
Automatic Standard Recognition by IC Software. This is not required if the built-in Automatic Standard Recognition System function is used (default).
Bit Name
BUS_EXP I2S_CO_EN I2S_DO_EN EN_STBY
Reset
0 0 0 0
Function
Static control by I2C of hardware pin BUS_EXP 0 = I2S Input (I2S_SCK , I2S_LR_CLK, I2S_PCM_CLK in input mode) 1 = I2S Output (I2S_SCK , I2S_LR_CLK, I2S_PCM_CLK in output mode) 0 = I2S Input (I2S_DATA0 in input mode) 1 = I2S Output (I2S_DATA0 in output mode) Standby mode enabling 0: Normal mode 1: To lock the digital signals before to settle the device in standby mode
CLOCK_DOWN Bit [2] SOFT_LRST1 SOFTR_RST
0 0 0 0
clock down of the dsp, decoder. Reserved Softreset (active high) of Decoder.. General softreset (active high) to reset all hardware registers except for I2C data.
I2S_CTRL
Address: 04h Type: R/W Bit 7 I2S_PLL Bit 6 SYNC_SIGN Bit 5 I2S_SRC
IS Synchronization Control Register
Bit 4
Bit 3
Bit 2 LOCK_MODE
Bit 1
Bit 0
LOCK_TH[1:0]
SYNC_CST[1:0]
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STV82X8
Register List
Bit Name
I2S_PLL
Reset
0
Function
Selects the i2s source for the synchronization with the synthesizer (at 48KHz only) 0: I2S_LR_CLK selected 1: I2SA_LR_CLK selected
SYNC_SIGN I2S_SRC
0 0
Reverse the sign of the loop - To be used in case of gain inversion of the Frequency Synthesizer Selects the i2s source for the src 0: I2S_LR_CLK selected 1: I2SA_LR_CLK selected
LOCK_TH[1:0]
00
Lock Detector Threshold Programming 00: 1 CLK period error of accumulation 01: 2 CLK period error of accumulation 10: 4 CLK period error of accumulation 11: 8 CLK period error of accumulation
LOCK_MODE
0
Lock Detector Mode 0: Lock when accumulation error within lock threshold and LR detected (period counter not saturated) 1: Lock when only accumulation error within lock threshold. Don't care of the LR detection
SYNC_CST[1:0]
00
Synchronization Time Constant Defines the measurement period of LR 00: Half period measured (lowest accuracy) 01: One full period measured 10: Two full periods measured 11: Four full periods measured (highest accuracy)
I2S_STAT
Address: 05h Type: R/W Bit 7 0 Bit 6 0 Bit 5 0
IS Synchronization Status Register
Bit 4 0
Bit 3 0
Bit 2 0
Bit 1 LR_OFF
Bit 0 LOCK_FLAG
Bit Name
Bits[7:2] LR_OFF
Reset
0 0 Reserved. LR Signal Detection 0: LR signal detected and correct 1: Missing LR pulses detected
Function
LOCK_FLAG
0
Lock Flag allowing unmute of Audio Output
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Register List I2S_SYNC_OFFSET
Address: 06h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
STV82X8 IS Synchronization Offset Frequency Register
Bit 0
I2S_SFO[7:0]
Bit Name
I2S_SFO[7:0]
Reset
0000 0000
Function
IS synchronization frequency offset (450 ppm full scale)
12.4
Clocking 1
A low-jitter PLL Clock is integrated and can be fully reprogrammed using the registers described below. By default, the programming is defined for a 27-MHz crystal oscillator, which is the frequency recommended for reducing potential RF interference in the application. However, if necessary, the PLL Clock can be re-programmed for other crystal oscillator frequencies within a range from 23 to 30 MHz. Other crystal frequencies can be programmed on your demand.
Note:
A Crystal Frequency change is compatible with other default IC programming including the built-in Automatic Standard Recognition System.
SYS_CONFIG
Address: 07h Type: R/W Bit 7 SYNC_PLL Bit 6 OPEN_PLL Bit 5
System Configuration Control Register
Bit 4
Bit 3
Bit 2
Bit 1 BIT[1:0]
Bit 0
INPUT_FREQ[3:0]
Bit Name
SYNC_PLL
Reset
0 Status of the loop wyth the synthesizer 0: Open 1: Closed
Function
OPEN_PLL
0
Force the loop with the synthesizer to be open 0: No Action 1: Loop Open
INPUT_FREQ[3:0]
0010
I2S Input frequency 0010: 48 kHz
BIT[1:0]
10
Reserved
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STV82X8 FS1_DIV
Address: 08h Type: R/W Bit 7 EN_PROG Bit 6 0 Bit 5 NDIV1[1:0] Bit 4 Bit 3 0 Bit 2 Bit 1 SDIV1[2:0]
Register List FS1 I/O Divider Programming Register
Bit 0
Bit Name
EN_PROG
Reset
0 FS1 programmation enable
Function
0: FS1 I2C registers programmation ignored by system - FS1 pre-programmed automatically by SYS-CONFIG register (normal use with standard oscillator of 27 MHz) 1: FS1 I2C registers programmation used by system - FS1 pre-programmation by SYS-CONFIG desactivated (to be used in case of no standard oscillator, other than 27 MHz) Bit 6 NDIV1[1:0] Bit 3 SDIV1[2:0] 0 01 0 011 Reserved. FS1 Input clock divider selection Reserved. FS1 Output clock divider selection
FS1_MD
Address: 09h Type: R/W Bit 7 0 Bit 6 0 Bit 5 0
FS1 Coarse Selection Register
Bit 4
Bit 3
Bit 2 MD1[4:0]
Bit 1
Bit 0
Bit Name
Bits[7:5] MD1[4:0]
Reset
000 10001 Reserved. FS1 Coarse Selection
Function
FS1_PE_H
Address: 0Ah Type: R/W Bit 7 Bit 6 Bit 5
FS1 Fine Selection Register (MSBs)
Bit 4 PE_H1[7:0]
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
PE_H1[7:0]
Reset
0011 0110 FS1 Fine Selection (MSBs)
Function
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Register List FS1_PE_L
Address: 0Bh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 PE_L1[7:0] Bit 3 Bit 2 Bit 1
STV82X8 FS1 Fine Selection Register (LSBs)
Bit 0
Bit Name
PE_L1[7:0]
Reset
0000 0000 FS1 Fine Selection (LSBs)
Function
12.5
Demodulator
DEMOD_CTRL Demodulator Control Register
Address: 0Ch Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 Bit 1 DEMOD_MODE[2:0] Bit 0
Bit Name
Bits [7:3] DEMOD_MODE[ 2:0]
Reset
00000 001 Reserved Demodulator Mode Select Demod FM 000: 001: Normal Wide
Function
other configuration: Reserved
DEMOD_STAT
Address: 0Dh Type: R Bit 7 0 Bit 6 0 Bit 5 0
Demodulator Detection Status Register
Bit 4
Bit 3
Bit 2
Bit 1 FM1_CAR
Bit 0 FM1_SQ
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STV82X8
Register List
Bit Name
Bits [7:2] FM1_CAR
Reset
000 0 Reserved. Channel 1 FM Carrier Detector Flag 0: Not detected 1: Detected
Function
FM1_SQ
0
Channel 1 FM Squelch Detector Flag 0: Not detected 1: Detected
Note:
These registers allow direct access to the demodulator signal detectors.
AGC_CTRL
Address: 0Eh Type: R/W Bit 7 0 Bit 6 0 Bit 5 IF_SELECT
IF AGC Control Register
Bit 4
Bit 3 AGC_REF[2:0]
Bit 2
Bit 1
Bit 0
AGC_CST[1:0]
Bit Name
Bits[7:5] IF_SELECT
Reset
00 0 Reserved. Selection of the IF input. 0: IF input SIF 1 1: IF input SIF 2
Function
AGC_REF[2:0]
100
This bitfield is used to defines the clipping level which adjusts the allowable proportion of samples at the input of the ADC which will be clipped. The AGC tries to maximize the use of the full scale range of the ADC. The default setting gives a ratio of 1/256. Clipping Ratio 000: 001: 010: 011: 1/16 (Single carrier) 1/32 1/64 1/128 100: 101: 110: 111: Clipping Ratio 1/256 (Default) 1/512 1/1024 1/2048 (Multiple carriers)
AGC_CST[1:0]
01
AGC Time Constant This is the time constant between each step of 1.5 dB by the AGC. Step Duration (ms) 00 01 10 11 1.33 2.66 5.33 10.66
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Register List AGC_GAIN
Address: 0Fh Type: R/W Bit 7 0 Bit 6 Bit 5 Bit 4 AGC_ERR[4:0] Bit 3 Bit 2 Bit 1 SIG_OVER
STV82X8 IF AGC Control and Status Register
Bit 0 SIG_UNDER
Bit Name
Bit 7 AGC_ERR[4:0]
Reset
0 00000 Reserved. Amplifier Gain Control
Function
This is the Gain Control value of AGC. There are 20 steps of +1.5 dB (see Note below). 00000: Gain-min 10100: Gain-min + 30 dB 11111: Gain-min + 30 dB SIG_OVER 0 AGC Input SIgnal Upper Threshold 0: Normal signal 1: Signal too large and AGC is overloaded SIG_UNDER 0 AGC Input SIgnal Lower Threshold 0: Normal signal 1: Signal too small and AGC is underloaded When the AGC is in Automatic mode (AGC_CMD = 0), bits SIG_OVER and SIG_UNDER indicate if the input signal is too small/large and the AGC is under/overloaded. This is useful when setting the STV82x7 SIF input level.
Note:
When AGC_CMD = 0, AGC_ERR[4:0] can be read -- indicating the input level. It can also be written to -- presetting the AGC level which will then adjust itself to the final value. When AGC_CMD = 1, the AGC is off and writing to AGC_ERR[4:0] directly controls the AGC amplifier gain. Reading AGC_ERR just confirms the fixed value.
DC_ERR_IF
Address: 10h Type: R Bit 7 Bit 6 Bit 5
DC Offset Status for IF ADC
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DC_ERR[7:0]
Bit Name
DC_ERR[7:0]
Reset
00000000 DC offset error of IF ADC output
Function
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STV82X8
Register List
12.6
Demodulator Channel 1
CARFQ1H, CARFQ1M, CARFQ1L Channel 1 Carrier DCO Frequency
Address: 12h to 14h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CARFQ1[23:16], CARFQ1[15:8], CARFQ1[7:0]
Bit Name
CARFQ1[23:16] CARFQ1[15:8] CARFQ1[7:0]
Reset
00101110 11100000 00000000
Function
Channel 1 DCO Carrier Frequency (8 MSBs) Channel 1 DCO Carrier Frequency Channel 1 DCO Carrier Frequency (8 LSBs), see Table 2.
Table 9: Mono Carrier Frequencies by System System
M/N
Mono Carrier Freq. (MHz)
4.5
CARFQ1[23:0] (dec)
3072000
CARFQ1[23:0]
2EE000h
Note:
Carrier Freq: CARFQ1(dec).fS / 224 with fS = 24.576 MHz (crystal oscillator frequency independent)
FIR1C[0:7]
Address: 15h to 1Ch Type: R/W Bit 7 Bit 6 Bit 5
Channel 1 FIR Coefficients
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FIR1C0[7:0] to FIR1C7[7:0]
Description Bitfield
(reset state) FM 27 kHz FIR1C0[7:0] FIR1C1[7:0] FIR1C2[7:0] FIR1C3[7:0] FIR1C4[7:0] FIR1C5[7:0] FIR1C6[7:0] FFh FEh FEh 00h 06h 0Eh 16h FM 50 kHz 00h FEh FCh FDh 02h 0Dh 18h FM 200 kHz 00h 01h 01h FCh 08h F6h F8h FM 350 kHz 02h 01h FCh 03h 04h F2h 06h FM 500 kHz 01h 00h 04h FAh 05h 00h F2h BTSC 01h 00h FEh FCh 00h 0Bh 19h
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Register List
STV82X8
Description Bitfield
(reset state) FM 27 kHz FIR1C7[7:0] 1Bh FM 50 kHz 1Fh FM 200 kHz 4Ah FM 350 kHz 43h FM 500 kHz 4Dh BTSC 24h
ACOEFF1
Channel 1 Baseband PLL Loop Filter Proportional Coefficient
Address: 1Dh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ACOEFF1[7:0]
Bit Name
ACOEFF1[7:0]
Reset
00100010
Function
Used to program the Proportional Coefficient of the baseband PLL loop filter (Channel 1) Defines the damping factor of the loop. For values, refer to Table 3.
BCOEFF1
Channel 1 Baseband PLL Loop Filter Integral Coefficient & DCO Gain
Address: 1Eh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
BCOEFF1[7:0]
Bit Name
BCOEFF1[7:0]
Reset
00001001
Function
Used to program the Integral Coefficient of the baseband PLL loop filter and DCO gain Defines the bandwidth of the loop. For values, refer to Table 3.
Table 10: Baseband PLL Loop Filter Adjustment (FM Mode) FM Mode
ACOEFF BCOEFF FM_DEV max (kHz) DCO Range (kHz)
Small
10h 1Ah 62.5 96
Standard
22h 12h 125 192
Medium
2Ch 0Ah 250 384
Wide*
2Ch 0Ah 500 768
BTSC
22h 09h 500 768
(*)
Refer to DEMOD_CTRL (DEMOD_MODE[2:0])
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STV82X8 CRF1
Address: 1Fh Type: R Bit 7 Bit 6 Bit 5 Bit 4 CRF1[7:0] Bit 3 Bit 2 Bit 1
Register List Channel 1 Baseband PLL Demodulator Offset
Bit 0
Bit Name
CRF1[7:0]
Reset
(00000000) Channel 1 Carrier Recovery Frequency
Function
Displays the instantaneous frequency offset of the Channel 1 Baseband PLL Demodulator.
CETH1
Address: 20h Type: R/W Bit 7 Bit 6 Bit 5
Channel 1 FM Carrier Level Threshold
Bit 4 CETH1[7:0]
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
CETH1[7:0]
Reset
00100000
Function
This register is used to compare the carrier level in the channel and the threshold value. This level is measured after the channel filter and is relative to the full scale reference level (0 dB). This is used as part of the validation of an FM signal, if the carrier level is below the threshold, the signal is considered to be non-valid. Recommended value is 10h. CETH FFh 80h 40h 20h Threshold (dB) -6 -12 -18 -24 (Default) CETH 10h 08h 00h Threshold (dB) -32 (Recommended Value) -38 OFF (all carrier levels are accepted)
SQTH1
Address: 21h Type: R/W Bit 7 Bit 6 Bit 5
Channel 1 FM Squelch Threshold Register
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SQTH1[7:0]
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Register List
STV82X8
Bit Name
SQTH1[7:0]
Reset
00111100
Function
The squelch detector measures the level of high frequency noise (> 40 kHz) and compares it to the threshold level (SQTH). If the level is below this value, the S/N of the FM signal is considered to be acceptable. Values are given for FM with standard deviation. SQTH FAh 77h 3Ch 23h 19h S/N (dB) 0 10 15 (Default) 20 25
CAROFFSET1
Address: 22h Type: R/W Bit 7 Bit 6 Bit 5
Channel 1 DCO Carrier Offset Compensation
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CAROFFSET1[7:0] (S)
Bit Name
CAROFFSET1[7:0]
Reset
00000000
Function
This value is used to correct the carrier frequency offset of the incoming IF signal. Automatic frequency control in FM mode can be implemented by registers DC_REMOVAL_L and DC_REMOVAL_R. A DCO frequency offset (in two's complement format) is added to the pre-programming value by AUTOTSD in the CARFQ1 registers (corresponding to the standard IF carrier frequency). The programmable carrier offset ranges from -192 kHz to +190.5 kHz with a resolution of 1.5 kHz. For standard FM deviation, the value displays by DC_REMOVAL_L and DC_REMOVAL_R can be directly loaded in CAROFFSET1 to exactly compensate the carrier offset on Channel 1
CHANNEL_GAIN
Address:45h Type: R/W Bit 7 0 Bit 6 0 Bit 5 0
Demodulator channel gain
Bit 4 0
Bit 3 0
Bit 2 0
Bit 1
Bit 0
CH_GAIN[1:0]
Bit Name
Bits[7:2]
Reset
000000 Reserved.
Function
Channel 1 Gain after the FM Demodulation CH_GAIN[1:0] 10 00: Gain 10: Gain*4 (Default) 01: Gain * 2 11: Gain *8
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STV82X8 STEREO_CONF
Address:43h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 FREQ_PIL
Register List BTSC Stereo Configuration
Bit 0 RESET
LOCK_TH_STE[7:4]
LOOP_GAIN[1:0]
Bit Name
LOCK_TH_STE[ 7:4]
Reset
0011 10 BTSC Lock Stereo Threshold Gain of Stereo PLL 00: Gain * 4 10: Gain (Default) 0 Pilot Frequency Selection 0: 15.625-15.734 kHz 0 Stereo Reset 1: Reset Active
Function
LOOP_GAIN[1:0]
01: Gain * 2 11: Gain / 2
FREQ_PIL
1: Reserved
RESET
STEREO_FSM_CONF
Address:44h Type: R/W Bit 7 0 Bit 6 0 Bit 5 BYPASS
BTSC Finite State Machine Configuration
Bit 4 FSM_OFF
Bit 3
Bit 2 GAIN_INI[2:0]
Bit 1
Bit 0 STE_DEM
Bit Name
BIT[7:6] BYPASS
Reset
00 0 Reserved. Bypass of the Stereo Block 0: Stereo Block is On 0 FSM Switch Off 0: FSM is On 111 0 Initial loop gain for FSM
Function
1: Stereo Block is Bypassed
FSM_OFF GAIN_INI[2:0] STE_DEM
1: FSM is Off. Gain set by IC
Stereo dematrix inside the stereo block (before DBX) 1: reset active
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Register List STEREO_LEVEL_H
Address:45h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
STV82X8 BTSC Threshold High for Stereo Detection
Bit 0
STE_LEV_H[7:0]
Bit Name
STE_LEV_H[7:0]
Reset
00100011 Threshold High for Stereo Detection
Function
If carrier level is > STE_LEV_H, stereo is detected
STEREO_LEVEL_L
Address:46h Type: R/W Bit 7 Bit 6 Bit 5
BTSC Threshold Low for Stereo Detection
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
STE_LEV_L[7:0]
Bit Name
STE_LEV_L[7:0]
Reset
00001100 Threshold Low for Stereo Detection
Function
If carrier level is SAP_CONF
Address:47h Type: R/W Bit 7 0 Bit 6 0 Bit 5 0
BTSC SAP Selection
Bit 4 0
Bit 3 0
Bit 2 0
Bit 1 0
Bit 0 SAP_SEL
Bit Name
bit[7:1] SAP_SEL
Reset
0000000 0 Reserved. Selection of the SAP 0: Stereo selected
Function
1: SAP is selected on second channel
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STV82X8 SAP_LEVEL_H
Address:48h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Register List BTSC Threshold High for SAP Detection
Bit 0
SAP_LEV_H[7:0]
Bit Name
SAP_LEV_H[7:0]
Reset
01010000 Threshold high for SAP detection
Function
If SAP signal level is > SAP_LEV_H, SAP is detected
SAP_LEVEL_L
Address:49h Type: R/W Bit 7 Bit 6 Bit 5
BTSC Threshold Low for SAP Detection
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SAP_LEV_L[7:0]
Bit Name
SAP_LEV_L[7:0]
Reset
00110000 Threshold low for SAP detection
Function
If sap signal level is STE_CAR_LEV
Address:4Ah Type: R Bit 7 Bit 6 Bit 5
BTSC Stereo Carrier Level
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
STE_CAR_LEV[7:0]
Bit Name
STE_CAR_LEV[7:0]
Reset
00000000 Stereo carrier level
Function
STE_PLL_STAT
Address:4Bh Type: R Bit 7 0 Bit 6 0 Bit 5
BTSC Stereo PLL Status
Bit 4 LOOP_GAIN[3:0]
Bit 3
Bit 2 OVER
Bit 1 LOCK_DET
Bit 0 STE_DET
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Register List
STV82X8
Bit Name
Bits[7:6] LOOP_GAIN[3:0] OVER
Reset
00 000 0 Reserved.
Function
Final FSM gain at the end of the stereo search process Overflow append in stereo search process 1: overflow
LOCK_DET
0
Stereo PLL lock status 0: no lock on pilot 1: lock on pilot or no pilot detected (no stereo)
STE_DET
0
Stereo Detection 0: no stereo dectected 1: stereo detected
STE_SAP_STAT
Address:4Ch Type: R Bit 7 0 Bit 6 OVER Bit 5 LOCK_DET
BTSC Stereo SAP Status
Bit 4 STE_DET
Bit 3 0
Bit 2 0
Bit 1 SQ_DET
Bit 0 SAP_DET
Bit Name
Bit 7 OVER
Reset
0 0 Reserved.
Function
Overflow append in stereo search process 1: overflow
LOCK_DET
0
Stereo PLL lock status 0: no lock on pilot 1: lock on pilot or no pilot detected (no stereo)
STE_DET bit[3:2] SQ_DET
0
Stereo detection 0: no stereo dectected 1: stereo detected
00 0
Reserved. Squelch detection of SAP 0: problem of noise 1: level of noise is good
SAP_DET
0
Signal detection of SAP 0: SAP not detected 1: SAP detected
PLL_P_G
Address:4Dh Type: R/W Bit 7 Bit 6 Bit 5
BTSC PLL Proportionnal Gain
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PLL_P_G[7:0]
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STV82X8
Register List
Bit Name
PLL_P_G[7:0]
Reset
01101100 PLL Proportional Gain
Function
PLL_I_G
Address:4Eh Type: R/W Bit 7 0 Bit 6 0 Bit 5 0
BTSC PLL Integral Gain
Bit 4 0
Bit 3
Bit 2
Bit 1
Bit 0
PLL_I_G[3:0]
Bit Name
Bits [7:4] PLL_I_G[3:0]
Reset
0000 0011 Reserved. PLL integral Gain
Function
SAP_SQ_TH
Address:4Fh Type: R/W Bit 7 Bit 6 Bit 5
SAP Squelch Threshold
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SAP_SQ_TH[7:0]
Bit Name
SAP_SQ_TH[7:0]
Reset
00110000 SAP squelch threshold
Function
12.7
I2S and Analog Control
I2S_ADC_CTRL I2S_DATA0 and ADC Input Selection and Power-up
Address: 56h Type: R/W Bit 7 Bit 6 I2S_DATA0_CTRL[2:0] Bit 5 Bit 4 0 Bit 3 ADC_ POWER_UP Bit 2 Bit 1 ADC_INPUT_SEL[2:0] Bit 0
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Register List
STV82X8
Bit Name
Reset
Source selection for output I2S_DATA0
Function
I2S_DATA0_CTRL[ 2:0]
000
000: LR 001: HP_LSS 010: LS_C and LS_SUB 011: SCART DAC Reserved.
100: S/PDIF_OUT 101: DELAY 110: reserved 111: reserved
Bit[4]
0
Control of the power up of the Audio ADC ADC_POWER_UP 1 0: ADC in power down mode 1: Wake up of the ADC Selection of the ADC input signal ADC_INPUT_SEL [2:0] 000 000: Input SCART 1 (Default) (B SDIP64)100: Input Mono 001: Input SCART 2 (res. SDIP 64) 101: Input SCART (res. TQFP) (A SDIP64) (1_BIS) 010: Input SCART 3 (res. SDIP 64) 110: Input SCART (5 TQFP100) (C SDIP64) (3_BIS) 011: Input SCART 4 (res. SDIP 64) 111: reserved (mute)
SCART1_2_OUTPUT_CTRL
Address: 57h Type: R/W Bit 7 SC2_MUTE Bit 6 Bit 5 SC2_OUTPUT_SEL[2:0]
SCART 1_2 Input Selection and Mute
Bit 4
Bit 3 SC1_MUTE
Bit 2
Bit 1 SC1_OUTPUT_SEL[2:0]
Bit 0
Bit Name
SC2_MUTE
Reset
Mute command for the output SCART 2 1 0: output not muted 1: output muted
Function
Selection of the output SCART 2 configuration: SC2_OUTPUT_ SEL[2:0] 010 000: DSP 001: Input Mono 010: Input SCART 1 (Def) (B SDIP 64) 011: Input SCART 2 (res. SDIP 64) 100: Input SCART 3 (res. SDIP 64) 101: Input SCART 4 (res. SDIP 64) 110: Input SCART (res. TQFP) (A SDIP 64) (1_BIS) 111: Input SCART (5 TQFP 100) (C SDIP 64) (3_BIS)
Mute command for the output SCART 1 SC1_MUTE 1 0: output not muted 1: output muted Selection of the output SCART 1 configuration: 000 000: DSP (Default) 001: Input Mono 010: Input SCART 1 (B SDIP 64) 011: Input SCART 2 (res SDIP 64) 100: Input SCART 3 (res. SDIP 64) 101: Input SCART 4 (res. SDIP 64) 110: Input SCART (res. TQFP) (A SDIP 64) (1_BIS) 111: Input SCART (5 TQFP100) (C SDIP64) (3_BIS)
SC1_OUTPUT_ SEL[2:0]
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STV82X8 SCART3_OUTPUT_CTRL
Address: 58h Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 SC3_MUTE Bit 2 Bit 1
Register List SCART 3 Input Selection and Mute
Bit 0
SC3_OUTPUT_SEL[2:0]
Bit Name
Bits[7:4]
Reset
0000 Reserved. Mute command for the output SCART 3
Function
SC3_MUTE
1
0: output not muted 1: output muted Selection of the output SCART 3 configuration:
SC3_OUTPUT_SE L[2:0] 011
000: DSP 100: Input SCART 3 (res. SDIP 64) 001: Input Mono 101: Input SCART 4 (res. SDIP 64) 010: Input SCART 1 (B SDIP) 110: Input SCART (res. TQFP) (A SDIP64) (1_BIS) 011: Input SCART 2 (Default) (res. SDIP 64)111: Input SCART (5 TQFP 100) (C SDIP 64) (3_BIS)
I2SO_DATA_CTRL
Address: 59h Type: R/W Bit 7 0 Bit 6 Bit 5 I2SO_DATA1_CTRL[2:0]
I2S Data Source Control
Bit 4
Bit 3 0
Bit 2
Bit 1 I2SO_DATA0_CTRL[2:0]
Bit 0
Bit Name
Bit [7]
Reset
0 000 Reserved.
Function
Source Selection for I2SO_DATA1 Output 000: Mute 001: LR 010: HP_LSS 011: LS_C and LS_SUB 100: SCART DAC 101: S/PDIF_OUT 110: Delay 111: Mute
I2SO_DATA1_CTRL [2:0]
Bit [3]
0 000
Reserved. Source Selection for I2SO_DATA0 Output 000: Mute 001: LR 010: HP_LSS 011: LS_C and LS_SUB 100: SCART DAC 101: S/PDIF_OUT 110: Delay 111: Mute
I2SO_DATA0_CTRL [2:0]
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Register List
STV82X8
12.8
Clocking 2
FS2_DIV FS2 I/O Divider Programming Register
Address: 5Ah Type: R/W Bit 7 0 Bit 6 0 Bit 5 NDIV2[1:0] Bit 4 Bit 3 Bit 2 Bit 1 SDIV2[2:0] Bit 0
Bit Name
Bit [7:6] NDIV2[1:0] Bit 4 SDIV2[2:0]
Reset
0 01 0 001 Reserved. FS2 Input clock divider selection Reserved. FS2 Output clock divider selection
Function
FS2_MD
Address: 5Bh Type: R/W Bit 7 0 Bit 6 0 Bit 5 0
FS2 Coarse Selection Register
Bit 4
Bit 3
Bit 2 MD2[4:0]
Bit 1
Bit 0
Bit Name
Bits[7:5] MD2[4:0]
Reset
000 10001 Reserved. FS2 Coarse Selection
Function
FS2_PE_H
Address: 5Ch Type: R/W Bit 7 Bit 6 Bit 5
FS2 Fine Selection Register (MSBs)
Bit 4 PE_H2[7:0]
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
PE_H2[7:0]
Reset
0101 1100 FS2 Fine Selection (MSBs)
Function
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STV82X8 FS2_PE_L
Address: 5Dh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 PE_L2[7:0] Bit 3 Bit 2 Bit 1
Register List FS2 Fine Selection Register (LSBs)
Bit 0
Bit Name
PE_L2[7:0]
Reset
0010 1001 FS2 Fine Selection (LSBs)
Function
12.9
DSP Control
HOST_CMD DSP Hardware Control
Address: 80h Type: R/W Bit 7 IT_IN_DSP Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 HW_RESET Bit 1 PATCH_WRIT E_ENABLE Bit 0 EMUL_SW
Bit Name
IT_IN_DSP Bits[6:3] HW_RESET Bits[1:0]
Reset
0 0000 0 00 Valid I2C table. Reserved. DSP Hardware reset when set. Reserved.
Function
IRQ_STATUS
Address: 81h Type: R/W Bit 7 IRQ7 Bit 6 IRQ6 Bit 5 IRQ5
IRQ Status
Bit 4 IRQ4
Bit 3 IRQ3
Bit 2 IRQ2
Bit 1 IRQ1
Bit 0 IRQ0
Bit Name
Bits[7:6] IRQ5 IRQ4
Reset
00 0 0 Reserved. Hp/Srnd DAC unmute ready HP detected
Function
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Register List
STV82X8
Bit Name
IRQ3 IRQ2 IRQ1 IRQ0
Reset
0 0 0 0 I2S SRC freq change detected I2S sync found IRQ I2S sync lost IRQ Auto-Standard IRQ
Function
FW_VERSION
Address: 82h Type: R Bit 7 Bit 6 Bit 5
Embedded Firmware Version
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FW_VERSION[7:0]
Bit Name
SOFT_VERSION [7:0]
Reset
0000 0011 Version of the Embedded software.
Function
ONCHIP_ALGOS
Address: 83h Type: R Bit 7 0 Bit 6 0 Bit 5
Display Algorithms available on the chip
Bit 4
Bit 3 TRUBASS
Bit 2 TRU SURROUND
Bit 1 PROLOGIC
Bit 0 MULTICHANN EL_OUT
PROLOGIC_T MULTI_I2S_IN YPE
Bit Name
Bits[7:6] PROLOGIC_TYPE MULTI_I2S_IN TRUBASS TRUSURROUND PROLOGIC MULTICHANNEL_O UT
Reset
00 0 0 0 0 0 0 Reserved. 0: ProLogic 1 1: ProLogic 2 0: 1 I2S input 1: 3 I2S inputs
Function
SRS TruBass algorithm is present when set. SRS TruSurround algorithm is present when set. Dolby Pro Logic algorithm is present when set. Multi-Channel output is present when set.
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STV82X8 DSP_STATUS
Address: 84h Type: R Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0
Register List DSP Status
Bit 0 INIT_MEM
Bit Name
Bits[7:1]
Reset
0000000 Reserved. DSP Initialization
Function
INIT_MEM
0
0: 1:
DSP is not initialized. DSP is initialized.
DSP_RUN
Address: 85h Type: R/W Bit 7 0 Bit 6 TEST_MODE_ INPUT Bit 5
DSP Configuration and Run
Bit 4
Bit 3
Bit 2
Bit 1 REGISTERS_ RESET
Bit 0 HOST_RUN
TEST_MODE
INPUT_CONFIG
Bit Name
Bits[7]
Reset
0 Reserved.
Function
active in TEST_MODE = 1 (bypass processing) 0: TEST_MODE_INP UT I2S_0 input -> L/R output I2S_1 input -> C/LFE output I2S_2 input -> Ls/Rs output I2S_0 input -> SCART output (-6dB) I2S_0 input -> L/R output I2S_0 input -> C/LFE output I2S_0 input -> Ls/Rs output I2S_0 input -> SCART output (-6dB) standard configuration bypass processing configuration Clock Loop test Not Used BTSC + I2S SRC + I2S DELAY + ADC BTSC + I2S 48K + I2S DELAY + ADC Not Used BTSC + MULTI I2S 48K + ADC I2C register table is not initialized when we soft reset I2C register table is initialized when we soft reset Soft Reset DSP Start DSP
0 1:
TEST_MODE[5:4]
00
00: 01: 10: 11: 00: 01: 10: 11: 0: 1: 0: 1:
INPUT_CONFIG
00
RESGISTERS_RE SET HOST_RUN
0 0
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Register List I2S_IN_CONFIG
Address: 86h Type: R/W Bit 7 LOCK_MODE _EN Bit 6 RESET_I2S Bit 5 SYNC Bit 4 LRCLK_START Bit 3 Bit 2 Bit 1 DATA_CFG
STV82X8 I2S Configuration
Bit 0 I2S_MODE
LRCLK_POLA SCLK_POLAR RITY ITY
Bit Name
LOCK_MODE_EN RESET_I2S
Reset
1 0 0: 1:
Function
Disable Lock Mode for external I2S input Enable Lock Mode for external I2S input
Reset I2S input sync when set I2S Synchronisation:
SYNC
0
0: 1:
Direct Capture Wait for Sync signal
according to LRCLK POLARITY, first data take: LRCLK_START 0 0: 1: Left Right
LRCLK_POLARITY SCLK_POLARITY DATA_CFG I2S_MODE
0 1 1 1
Polarity of the left data 0: 1: 0: 1: 0: 1: Falling Edge Rising Edge LSB First MSB First Not Standard Mode Standard Mode
Note:
This register must be set before the Start of the Software (85h: HOST_RUN = 1).
I2S_IN_SHIFT_RIGHT
Address: 87h Type: R/W Bit 7 0 Bit 6 0 Bit 5 0
I2S Shift Right
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SHIFT_RIGHT_RANGE[4:0]
Bit Name
Bits [7:5] SHIFT_RIGHT_RA NGE[4:0]
Reset
000 01000 Reserved
Function
Define the shift right to apply to 32-bit input samples. Range: 0 to 31
Note:
This register has to be set before the Start of the Software (0x85 : HOST_RUN = 1).
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STV82X8 I2S_IN_MASK
Address: 88h Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 Bit 3 Bit 2 WORD_MASK[4:0] Bit 1
Register List I2S Mask
Bit 0
Bit Name
Bits [7:5] WORD_MASK[4:0]
Reset
000 11111 Reserved
Function
Define the mask to apply to 32-bit input samples. Range: 0 to 31
Note:
This register has to be set before the Start of the Software (0x85 : HOST_RUN = 1).
I2S_IN_STATUS
Address: 89h Type: R/W Bit 7 Bit 6 Bit 5
SRC I2S Input Behaviour
Bit 4
Bit 3
Bit 2
Bit 1 I2S_INPUT_FREQ
Bit 0
ENABLE_IRQ ENABLE_IRQ AUTO_SRC_S ENABLE_IRQ _SRC_FREQ_ _SYNC_FOUN YNC _SYNC_LOST CHANGE D
Bit Name
AUTO_SRC_SYNC
Reset
0
Function
Allow the DSP to reset the SRC input DMA when an input freq change is detected. (Working in SRC mode only) 0: 1: no reset on input frequency change reset on input frequency change
ENABLE_IRQ_SRC _FREQ_CHANGE
0
Generate an IRQ3 when a frequency change is detected on SRC input. (Working in SRC mode only) 0: 1: IRQ3 generation not active IRQ3 generation active
ENABLE_IRQ_SYN C_FOUND
0
Generate an IRQ2 when a signal is synchronized on SRC input. (Working in SRC mode only) 0: 1: IRQ2 generation not active IRQ2 generation active
ENABLE_IRQ_SYN C_LOST
0
Generate an IRQ1 when a signal is lost on SRC input. (Working in SRC mode only) 0: 1: IRQ1 generation not active IRQ1 generation active
Bits [3] I2S_INPUT_FREQ
0 (000)
Reserved Display the frequency detected on SRC input 000: 001: 010: 011: no signal locked on SRC input 32 kHz 44.1 kHz 48 kHz 100: 101: 110: 111: signal locked but frequency unknown not used not used not used
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Register List
STV82X8
12.10 Automatic Standard Recognition
AUTOSTD_CTRL
Address: 8Ah Type: R/W Bit 7 SINGLE_SHOT Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 SAP_CHECK Bit 1 Bit 0
Automatic Standard Recognition Control
MONO_SAP_C FORCE_SQ_S FORCE_SQ_M AUTO_MUTE TRL_MATRIX AP ONO
STEREO_CHE MONO_CHEC CK K
Bit Name
SINGLE_SHOT
Reset
Function
Single-shot mode (To be selected whith any of the Mono/Stereo or Sap check bits):
0
0: 1:
Single Shot mode is not selected Single Shot mode is selected1
MON_SAP_CONTR OL_MATRIX
Change the behaviour of the automatic matrix control for SAP language 0 0: 1: When SAP signal is detected, SAP signal is outputed on both Left and Right channels When SAP signal is detected, Mono signal is outputed on the Left channel and SAP signal is outputed on the Right channe
FORCE_SQ_SAP 0
Force the squelch status during SAP detection by autostandard. 0: 1: SAP squelch from demod status SAP squelch forced to 1
FORCE_SQ_MON O
Force the squelch status during MONO detection by autostandard. 0 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: MONO squelch from demod status MONO squelch forced to 1 Output channels are never mutted Output channels are automaticly muted when no signal is detected No SAP standard research SAP standard research No STEREO standard research STEREO standard research (priority is given to SAP if selected) No MONO standard research (AutoStandard OFF) MONO standard research (mandatory to activate Autostandard)
AUTO_MUTE SAP_CHECK STEREO_CHECK MONO_CHECK
0 0 0 0
1. Single_Shot mode will pre-program demodulator registers in a choosen standard (bits b2, b1, b0). Autostandard will be switched OFF (Mono_check = 0) after the programation of the registers.
AUTOSTD_TIME
Address: 8Bh Type: R/W Bit 7 0 Bit 6 0 Bit 5 0
Detection Time Out
Bit 4
Bit 3 STEREO_TIME[2:0]
Bit 2
Bit 1
Bit 0
FM_TIME[1:0]
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STV82X8
Register List
Bit Name
Bits [7:5] STEREO_TIME[2:0]
Reset
000 Reserved Stereo Detection Time-out 000 000: 001: 010: 011: 20 ms (Default) 40 ms 100 ms 200 ms 100: 101: 110: 111: 400 ms 800 ms 1200 ms 1600 ms
Function
FM_TIME[1:0] 10
FM Detection Time-out 00: 16 ms 01: 32 ms 10: 48 ms (Default) 11: 64 ms
Note:
The time-out default value is optimum and does not normally need to be changed.
AUTOSTD_STATUS
Address: 8Ch Type: R Bit 7 0 Bit 6 0 Bit 5 0
Detection Standard Status
Bit 4 0
Bit 3 SAP_OK
Bit 2 STEREO_OK
Bit 1 MONO_OK
Bit 0 AUTOSTD_ON
Bit Name
Bits[7:4] SAP_OK
Reset
0000 Reserved. SAP Standard Recognition Status 0 0: 1: SAP Standard not detected SAP Standard detected
Function
STEREO_OK 0
Stereo Standard Recognition Status 0: 1: Stereo Standard not detected Stereo Standard detected
MONO_OK 0
Mono Standard Recognition Status 0: 1: Mono Standard not detected Mono Standard detected
AUTOSTD_ON 0
Automatic Standard Recognition System Status 0: 1: Automatic Standard Recognition System is OFF Automatic Standard Recognition System is ON
AUTOSTD_DEM_STATUS
Address: 8Dh Type: R Bit 7 0 Bit 6 OVERFLOW Bit 5 LCK_DET
Demodulator Status
Bit 4 ST_DET
Bit 3 SAP_SQ
Bit 2 SAP_DET
Bit 1 FM1_CAR
Bit 0 FM1_SQ
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Register List
STV82X8
Bit Name
Bits[7] LCK_DET ST_DET SAP_SQ SAP_DET FM1_CAR FM1_SQ
Reset
0 0 0 0 0 0 0 Reserved. 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: Stereo Lock Not Detected Stereo Lock Detected Stereo Not Detected Stereo Detected SAP Squelch Not Detected SAP Squelch Detected SAP Not Detected SAP Detected FM1 Carrier Not Detected FM1 Carrier Detected FM1 Squelch Not Detected FM1 Squelch Detected
Function
DMA_FORCE_OFF
Address: 8Eh Type: R Bit 7 0 Bit 6 0 Bit 5 0
Input DMA disable
Bit 4 ADC
Bit 3 I2S2
Bit 2 I2S1
Bit 1 I2S0
Bit 0 DEMOD
Bit Name
Bits[7:5] ADC I2S2 I2S1 I2S0 DEMOD
Reset
000 0 0 0 0 0 Reserved. 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: ADC input DMA active ADC input DMA not active I2S2 input DMA active I2S2 input DMA not active I2S1 input DMA active I2S1 input DMA not active I2S0 input DMA active I2S0 input DMA not active Demod input DMA active Demod input DMA not active
Function
Note:
This register must be set before the Start of the Software (85h: HOST_RUN = 1).
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STV82X8 I2S_IN_DELAY_CONFIG
Address: 8Fh Type: R/W Bit 7 0 Bit 6 0 Bit 5 SYNC Bit 4 LRCLK_START Bit 3 Bit 2 Bit 1 DATA_CFG
Register List I2S Configuration for Delay Input
Bit 0 I2S_MODE
LRCLK_POLA SCLK_POLAR RITY ITY
Bit Name
Bits[7:6]
Reset
00 Reserved. IS Synchronisation:
Function
SYNC
0
0: 1:
Direct Capture Wait for Sync signal
LRCLK_START 0
according to LRCLK POLARITY, first data take: 0: 1: Left Right
LRCLK_POLARITY SCLK_POLARITY DATA_CFG I2S_MODE
0 1 1 1
polarity of the left data 0: 1: 0: 1: 0: 1: Falling Edge Rising Edge LSB First MSB First Not Standard Mode Standard Mode
Note:
For this input, the SHIFT_RIGHT and MASK of the I2S input are set. SHIFT_RIGHT = 0x08 MASK = 0x1F
12.11 Demodulator
BTSC_FINE_PRESCALE_ST
Address: 90h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
BTSC input prescale for Stereo Mode
BTSC_FINE_PRESCALE_ST[7:0] (S)
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Register List
STV82X8
Bit Name
Reset
Function
Set the prescale of the signal coming from the demodulator when STEREO is demodulated in order to optimize the signal level at DBX block input (steps of 0.02 dB):
BTSC_FINE_PRES CALE_ST[7:0]
0000 0000
1000 0000: ... 0000 0000: 0000 0001: ... 0111 1111:
-2.56 dB 0 dB 0.02 dB 2.54 dB
BTSC_FINE_PRESCALE_SAP
Address: 91h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4
BTSC Input Prescale for SAP Mode
Bit 3
Bit 2
Bit 1
Bit 0
BTSC_FINE_PRESCALE_SAP[7:0] (S)
Bit Name
Reset
Function
Set the prescale of the signal coming from the demodulator when SAP is demodulated in order to optimize the signal level at DBX block input (steps of 0.02 dB):
BTSC_FINE_PRES CALE_SAP[7:0]
0000 0000
1000 0000: ... 0000 0000: 0000 0001: ... 0111 1111:
-2.56 dB 0 dB 0.02 dB 2.54 dB
BTSC_CONTROL
Address: 92h Type: R Bit 7 FINE_PRESC ALE_SELECT _SAP Bit 6 Bit 5
BTSC Back-end Decoder Control
Bit 4 DBX_ON
Bit 3
Bit 2
Bit 1
Bit 0
DBX_DEMATRIX[1:0]
DEEMPHASIS_CH1[1:0]
DEEMPHASIS_CH0[1:0]
Bit Name
FINE_PRESCALE_ SELECT_SAP
Reset
Function
Select the prescale value to apply on second channel before DBX
0
0: 1:
STEREO prescale (register 90h) SAP prescale (register 91h)
DBX_DEMATRIX[ 1:0]
Select L/R Dematrix for STEREO standard 00 00: No dematrixing (Mono or SAP) 01: L/R Dematrix (STEREO): L=Ch0+(Ch1)/2, R=Ch0-(Ch1)/2 0: 1: 10: Reserved 11: Reserved
DBX_ON
0
DBX noise reductor not active DBX noise reductor active on second channel (STEREO or SAP)
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STV82X8
Register List
Bit Name
DEEMPHASIS_CH 1[1:0]
Reset
Function
Select the demmphasis for demodulator second channel :
00
00: No De-emphasis 01: 25 s De-emphasis
10: 50 s De-emphasis 11: 75 s De-emphasis
DEEMPHASIS_CH 0[1:0]
Select the demmphasis for demodulator first channel : 00 00: No De-emphasis 01: 25 s De-emphasis 10: 50 s De-emphasis 11: 75 s De-emphasis
DC_REMOVAL
Address: 93h Type: R Bit 7 0 Bit 6 0 Bit 5
DC Removal
Bit 4
Bit 3 0
Bit 2
Bit 1
Bit 0
DEEMPHASIS DBX_FILTER_ _FILTER_SEL SELECT ECT
DC_DEMOD_ DC_DEMOD_ DC_SCART_O POST_ON PRE_ON N
Bit Name
Bits[7:6] DBX_FILTER_SEL ECT
Reset
00 Reserved.
Function
Select the type of filter used in the DBX block 1 0: 1: 1st Order Filter De-emphasis 2nd Order Filter De-emphasis
DEMPHASIS_FILT ER_SELECT
Select the type of filter used in the De-emphasis block 1 0: 1: 1st Order Filter De-emphasis 2nd Order Filter De-emphasis
Bit[3] DC_DEMOD_POST _ON
0
Reserved Control the DC removal placed on the demod path, AFTER the DBX block:
0
0: 1:
DC removal OFF DC Removal ON
DC_DEMOD_PRE_ ON
Control the DC removal placed on the demod path, BEFORE the DBX block: 0 0: 1: DC removal OFF DC Removal ON
DC_SCART_ON 0
Control the DC removal placed on the SCART path: 0: 1: DC removal OFF DC Removal ON
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Register List
STV82X8
12.12 Audio PreProcessing & Selection
PRESCALE_DEMOD_MONO
Address: 94h Type: R/W Bit 7 PRESCALE_D EMOD_SELEC T_SAP Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Prescale for Demod MONO
PRESCALE_DEMOD_MONO[6:0] (S)
Bit Name
PRESCALE_DEMO D_SELECT_SAP
Reset
Function
Select the prescale value to apply on channel 0 (Mono/Stereo): 0:
0 1: PRESCALE_DEMO D_MONO[6:0]
Apply STEREO Prescale (95h) to the demodulated signal. To be used in case of STEREO demodulation. Apply MONO Prescale (94h) on left channel and SAP Prescale (96h) on right channel to the demodulated signal. To be used in case of MONO or SAP demodulation.
Set the prescale of the signal coming from the demodulator when MONO (Channel 0): 101 0000: ... 000 0000 000 0000: 000 0001: ... 011 0000: -12 dB 0 dB 0.5 dB 24 dB
PRESCALE_DEMOD_STEREO
Address: 95h Type: R/W Bit 7 0 Bit 6 Bit 5 Bit 4
Prescale for Stereo Demodulation
Bit 3
Bit 2
Bit 1
Bit 0
PRESCALE_DEMOD_STEREO[6:0] (S)
Bit Name
Bits[7] PRESCALE_DEMO D_STEREO[6:0]
Reset
0 Reserved.
Function
Sets the prescale value of the Stereo signal coming from the demodulator (Channels 0 and 1): 101 0000: ... 000 0000 000 0000: 000 0001: ... 011 0000: -12 dB 0 dB 0.5 dB 24 dB
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STV82X8 PRESCALE_DEMOD_SAP
Address: 96h Type: R/W Bit 7 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Register List Prescale for SAP Demodulation l
Bit 0
PRESCALE_DEMOD_SAP[6:0] (S)
Bit Name
Bits[7] PRESCALE_DEMO D_SAP[6:0]
Reset
0 Reserved.
Function
Set the prescale of the signal coming from the demodulator when SAP (channel 0): 101 0000: ... 000 0000 000 0000: 000 0001: ... 011 0000: -12dB 0dB 0.5dB 24dB
PRESCALE_SCART
Address: 97h Type: R/W Bit 7 0 Bit 6 Bit 5
Prescale for SCART
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PRESCALE_SCART[6:0] (S)
Bit Name
Bits[7] PRESCALE_SCAR T[6:0]
Reset
0 Reserved.
Function
Set the prescale of the signal coming from the SCART ADC: 101 0000: ... 000 0000 000 0000: 000 0001: ... 011 0000: -12dB 0dB 0.5dB 24dB
PRESCALE_I2S0
Address: 98h Type: R/W Bit 7 0 Bit 6 Bit 5
Prescale for I2S0
Bit 4
Bit 3 PRESCALE_I2S0[6:0] (S)
Bit 2
Bit 1
Bit 0
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Register List
STV82X8
Bit Name
Bits[7] PRESCALE_I2S0[ 6:0]
Reset
0 Reserved.
Function
Set the prescale of the signal coming from the I2S0 (SRC input or I2S0 in multichannel input mode): 101 0000: 000 0000 ... 000 0000: 000 0001: ... 011 0000: -12dB 0dB 0.5dB 24dB
PRESCALE_I2S1
Address: 99h Type: R/W Bit 7 0 Bit 6 Bit 5
Prescale for I2S1
Bit 4
Bit 3 PRESCALE_I2S1[6:0] (S)
Bit 2
Bit 1
Bit 0
Bit Name
Bits[7] PRESCALE_I2S1[ 6:0]
Reset
0 Reserved.
Function
Set the prescale of the signal coming from the I2S1 (I2S1 in multichannel input mode): 101 0000: ... 000 0000 000 0000: 000 0001: ... 011 0000: -12dB 0dB 0.5dB 24dB
PRESCALE_I2S2
Address: 9Ah Type: R/W Bit 7 0 Bit 6 Bit 5
Prescale for I2S2
Bit 4
Bit 3 PRESCALE_I2S2[6:0] (S)
Bit 2
Bit 1
Bit 0
Bit Name
Bits[7] PRESCALE_I2S2[ 6:0]
Reset
0 Reserved.
Function
Set the prescale of the signal coming from the I2S2 (delay input or I2S2 in multichannel input mode): 101 0000: 000 0000 ... 000 0000: 000 0001: ... 011 0000: -12dB 0dB 0.5dB 24dB
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STV82X8 PEAK_DETECTOR
Address: 9Bh Type: R Bit 7 0 Bit 6 Bit 5 PEAK_L_R_RANGE[2:0] Bit 4 Bit 3 Bit 2 PEAK_DET_INPUT[2:0] Bit 1
Register List Peak Detector
Bit 0 PEAK_DETEC TOR_ON
Bit Name
Bits[7] PEAK_L_R_RANG E[2:0]
Reset
0 Reserved.
Function
Control the sensitivity of the "Left - Right" peak measurement (register 0x9E). The difference between Left and Right signal is sometime very small (in case of mono input for example), so we can multiply the "Left - Right" peak measurement in order to add precision: 000 000: 001: 010: 011: Left - Right (Left - Right) x 2 (Left - Right) x 4 (Left - Right) x 8 100: 101: 110: 111: (Left - Right) x 16 (Left - Right) x 32 (Left - Right) x 64 (Left - Right) x 128
PEAK_DETECTOR _INPUT[2:0] 000
Select the input on which the peak detector makes the measurement: 000: 001: 010: 011: demod signal I2S0 signal I2S1 signal I2S2 signal 100: 101: 110: 111: SCART signal reserved reserved reserved
PEAK_DETECTOR _ON
Control the Peak detector: 0 0: 1: Peak detector OFF Peak detector ON
PEAK_L
Address: 9Ch Type: R/W Bit 7 OVERLOAD_L Bit 6 Bit 5
Peak Detector Left Channel
Bit 4
Bit 3 PEAK_L[6:0] (S)
Bit 2
Bit 1
Bit 0
Bit Name
OVERLOAD_L PEAK_L[6:0]
Reset
0
Function
This bit is set to 1 by the DSP when the Left peak detector reaches its maximum value (0x7F). It can be reset to 0. Displays the Absolute Peak Level of the Left channel of the audio source selected. The measured value is updated continuously every 64 ms. The range varies linearly from the full scale (0 dB) down to 1/256 of the full scale (-48 dB).
000 0000:<-36dBFS ... 000 0000 000 0001:-36dBFS ... 000 0011:-30dBFS ... 000 0111:-24dBFS ...
000 1111:-18dBFS ... 001 1111:-12dBFS ... 011 1111:-6dBFS ... 111 1111:0dBFS
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Register List PEAK_R
Address: 9Dh Type: R/W Bit 7 OVERLOAD_R Bit 6 Bit 5 Bit 4 Bit 3 PEAK_R[6:0] (S) Bit 2 Bit 1
STV82X8 Peak Detector Right Channel
Bit 0
Bit Name
OVERLOAD_R PEAK_R[6:0]
Reset
0
Function
This bit is set to 1 by the DSP when the Right peak detector reaches its maximum value (0x7F). It can be reset to 0. Displays the Absolute Peak Level of the Right channel of the audio source selected. The measured value is updated continuously every 64 ms. The range varies linearly from the full scale (0 dB) down to 1/256 of the full scale (-48 dB).
000 0000:<-36dBFS ... 000 0000 000 0001:-36dBFS ... 000 0011:-30dBFS ... 000 0111:-24dBFS ...
000 1111:-18dBFS ... 001 1111:-12dBFS ... 011 1111:-6dBFS ... 111 1111:0dBFS
PEAK_L_R
Address: 9Eh Type: R/W Bit 7 OVERLOAD_L _R Bit 6 Bit 5
Peak Detector Left Minus Right Channel
Bit 4
Bit 3 PEAK_L_R[6:0] (S)
Bit 2
Bit 1
Bit 0
Bit Name
OVERLOAD_L_R
Reset
0
Function
This bit is set to 1 by the DSP when the "Left-Right" peak detector reaches its maximum value (0x7F). It can be reset to 0. Displays the Difference between L and R (L - R) channels for the audio source selected:
PEAK_L_R[6:0]
000 0000:<-36dBFS ... 000 0001:-36dBFS 000 0000 ... 000 0011:-30dBFS ... 000 0111:-24dBFS ...
000 1111:-18dBFS ... 001 1111:-12dBFS ... 011 1111:-6dBFS ... 111 1111:0dBFS
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STV82X8
Register List
12.13 Matrixing
DOWNMIX_MODE
Address: 9Fh Type: R/W Bit 7 LT_RT_OUT_M ODE Bit 6 Bit 5 MIX_OUT_MODE[2:0] Bit 4 Bit 3 LFE_IN Bit 2 Bit 1 MIX_IN_MODE[2:0] Bit 0
Downmix Mode Configuration
Bit Name
LT_RT_OUT_MOD E
Reset
Define to format for downmix Lt/Rt output: 0 0: 1: Lt/Rt Prologic compatible mode L/R stereo mode
Function
MIX_OUT_MODE[ 2:0] LFE_IN
111
Select output channels configuration for downmix: see table 3. To select if LFE is inputed on I2S1 in multichannel input mode:
1
0: 1:
No LFE on I2S1 input LFE on I2S1 input
MIX_IN_MODE[2:0]
111
Select input channels configuration for downmix: see table 2.
Table 11: DownMix IN modes Parameter Coding (bin)
000 001 010 011 100 101 110 111
Parameter Field Lebel
MODE11 MODE10 MODE20 MODE30 MODE21 MODE31 MODE22 MODE32 not used 1/0 (C) 2/0 (L,R) 3/0 (L,R,C) 2/1 (L,R,S) 3/1 (L,R,C,S)
Function
2/2 (L,R,Ls,Rs) 3/2 (L,R,C,Ls,Rs)
Table 12: DownMix OUT modes Parameter Coding (bin)
000 001 010
Parameter Field Lebel
MODE20t MODE10 MODE20
Function
2/0 Dolby Surround (Lt,Rt) 1/0 (C) 2/0 (L,R)
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Register List
Table 12: DownMix OUT modes (Continued) Parameter Coding (bin)
011 100 101 110 111
STV82X8
Parameter Field Lebel
MODE30 MODE21 MODE31 MODE22 MODE32 3/0 (L,R,C) 2/1 (L,R,S) 3/1 (L,R,C,S)
Function
2/2 (L,R,Ls,Rs) 3/2 (L,R,C,Ls,Rs)
DOWNMIX_DUAL_MODE
Address: A0h Type: R/W Bit 7 0 Bit 6 0 Bit 5 0
Downmix Dual Mode Configuration
Bit 4 DUAL_ON
Bit 3
Bit 2
Bit 1
Bit 0
LS_DUAL_SELECT[1:0]
LTRT_DUAL_SELECT[1:0]
Bit Name
Bits[7:5] DUAL_ON
Reset
000 Reserved.
Function
0
Select dual mode for DownMix bloc in case of dual language (in dual mode, Input and output mode are forced to 2_0): 0: 1: Standard DownMix DownMix in Dual Mode
LS_DUAL_SELECT [1:0]
Select the language for LS output in case of Dual mode: 00 00: Stereo 01: Left mono 10: Right mono 11: Left + Right mix
LTRT_DUAL_SELE CT[1:0]
Select the language for LtRt output in case of Dual mode: 00 00: Stereo 01: Left mono 10: Right mono 11: Left + Right mix
DOWNMIX_CONFIG
Address: A1h Type: R/W Bit 7 0 Bit 6 0 Bit 5
Downmix Configuration
Bit 4
Bit 3
Bit 2
Bit 1 LR_UPMIX
Bit 0 NORMALIZE
SRND_FACTOR[1:0]
CENTER_FACTOR[1:0]
Bit Name
Bits[7:6] SRND_FACTOR [1:0]
Reset
00 00 Reserved 00: -3 dB 01: -4.5 dB 10: -6 dB 10: -6 dB
Function
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STV82X8
Register List
Bit Name
Reset
00: -3 dB 01: -4.5 dB 0: 1: 0: 1: 10: -6 dB 11: -4.5 dB
Function
CENTER_FACTOR 00 [1:0] LR_UPMIX NORMALIZE 0 1
Upmixing disabled Upmixing enabled (DTS specified) Normalization disabled Nnormalization enabled
AUDIO_MATRIX1
Address: A2h Type: R/W Bit 7 0 Bit 6 0 Bit 5
AudioMatrix Configuration Register
Bit 4 HP_OUT
Bit 3
Bit 2
Bit 1 LS_OUT
Bit 0
Bit Name
Bits[7:6] HP_OUT[1:0] LS_OUT[1:0]
Reset
00 010 010 Reserved
Function
Select the source to output on HP. See table 4. Select the source to output on LS. See table 4.
AUDIO_MATRIX2
Address: A3h Type: R/W Bit 7 0 Bit 6 0 Bit 5
AudioMatrix part configurationr
Bit 4 SCART2_OUT
Bit 3
Bit 2
Bit 1 SCART1_OUT
Bit 0
Bit Name
Bits[7:6] SCART2_OUT [1:0] SCART1_OUT [1:0]
Reset
00 010 Reserved Select the source to output on SCART2: see table 4. 010 Select the source to output on SCART1: see table 4.
Function
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Register List AUDIO_MATRIX3
Address: A4h Type: R/W Bit 7 0 Bit 6 0 Bit 5 Bit 4 SPDIF_OUT Bit 3 Bit 2 Bit 1 DELAY_OUT
STV82X8 AudioMatrix part configuration
Bit 0
Bit Name
Bits[7:6] SPDIF_OUT[1:0] DELAY_OUT[1:0]
Reset
00 010 010 Reserved.
Function
Select the source to output on SPDIF. See table 4. Select the source to output on DELAY. See table 4.
Table 13: AudioMatrix Input Sources Parameter Coding (bin)
000 001 010 011 100 101 110 111
Parameter Field Lebel
MUTE DELAY DEMOD LtRt I2S SCART Mute Output Delay Input
Function
BTSC Demod Input Downmix LtRt Input I2S Input SCART Input Reserved Reserved
CHANNEL_MATRIX_LS
Address: A5h Type: R/W Bit 7 Bit 6 Bit 5 0
Channel Matrix Configuration
Bit 4 0
Bit 3 0
Bit 2
Bit 1 CM_MATRIX_LS[2:0]
Bit 0
AUTOSTD_CT AUTOSTD_CT RL_LS RL_SPDIF
Bit Name
AUTOSTD_CTRL_L 0 S
Reset
Function
If this bit is activated, Autostandard algorithm will select automaticaly the appropriate matrixing (Bits[2:0]) for LS output channels depending on the detected standard (see table 6). 0: 1: Manual Matrix Selection Automatic Matrix Selection if AutoStandard is ON
Note: Automatic Matrix Selection must be used only when DEMOD signal is directed to the Matrix.
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STV82X8
Register List
Bit Name
AUTOSTD_CTRL_ SPDIF 0
Reset
Function
If this bit is activated, Autostandard algorithm will select automaticaly the appropriate matrixing (bits[2:0]) for SPDIF output channels depending on the detected standard (see table 6). 0: 1: Manual Matrix Selection Automatic Matrix Selection if AutoStandard is ON
Note: Automatic Matrix Selection must be used only when DEMOD signal is directed to the Matrix. Bits[5:3] CM_MATRIX_LS[ 2:0] 000 0000 Reserved Select the matrixing for the LS channels. See table 5.
CHANNEL_MATRIX_HP
Address: A6h Type: R/W Bit 7 AUTOSTD_CT RL_HP Bit 6 Bit 5
Channel Matrix Configuration
Bit 4
Bit 3
Bit 2
Bit 1 CM_MATRIX_HP[2:0]
Bit 0
CM_SOURCE_HP[1:0]
CM_POSITION_HP[1:0]
Bit Name
AUTOSTD_CTRL_ HP 0
Reset
Function
If this bit is activated, Autostandard algorithm will select automaticaly the appropriate matrixing (bits[2:0]) for HP output channels depending on the detected standard (see table 6). 0: 1: Manual Matrix Selection Automatic Matrix Selection if AutoStandard is ON
Note: Automatic Matrix Selection must be used only when DEMOD signal is directed to the Matrix. CM_SOURCE_HP[ 00 2:0] CM_POSITION_HP 00 [1:0] CM_MATRIX_HP[ 2:0] 0000 Select the source to copy on HP channel. See table 7. Select the position for the HP matrix. See block diagram Select the matrixing for the HP channels. See table 5.
CHANNEL_MATRIX_SCART1 Channel Matrix configuration
Address: A7h Type: R/W Bit 7 AUTOSTD_CT RL_SCART1 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 CM_MATRIX_SCART1[2:0] Bit 0
CM_SOURCE_SCART1[1:0]
CM_POSITION_SCART1[1:0]
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Register List
STV82X8
Bit Name
AUTOSTD_CTRL_ SCART1 0
Reset
Function
If this bit is activated, Autostandard algorithm will select automaticaly the appropriate matrixing (Bits[2:0]) for SCART1 output channels depending on the detected standard (see table 6). 0: 1: Manual Matrix Selection Automatic Matrix Selection if AutoStandard is ON
Note: Automatic Matrix Selection must be used only when DEMOD signal is directed to the Matrix. CM_SOURCE_SCA 00 RT1[2:0] CM_POSITION_SC 00 ART1[1:0] CM_MATRIX_SCA RT1[2:0] 0000 Select the source to copy on SCART1 channel. See table 7. Select the position for the SCART1 matrix. See block diagram Select the matrixing for the SCART1 channels. See table 5.
CHANNEL_MATRIX_SCART2 Channel Matrix configuration
Address: A8h Type: R/W Bit 7 AUTOSTD_CT RL_SCART2 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 CM_MATRIX_SCART2[2:0] Bit 0
CM_SOURCE_SCART2[1:0]
CM_POSITION_SCART2[1:0]
Bit Name
Reset
Function
If this bit is activated, Autostandard algorithm will select automaticaly the appropriate matrixing (Bits[2:0]) for SCART2 output channels depending on the detected standard (see table 6).
AUTOSTD_CTRL_ SCART2
0
0: 1:
Manual Matrix Selection Automatic Matrix Selection if AutoStandard is ON
Note: Automatic Matrix Selection must be used only when DEMOD signal is directed to the Matrix. CM_SOURCE_SCA RT2[2:0] CM_POSITION_SC ART2[1:0] CM_MATRIX_SCA RT2[2:0] 00 00 0000 Select the source to copy on SCART2 channel. See table 7. Select the position for the SCART2 matrix. See block diagram Select the matrixing for the SCART2 channels. See table 5.
CHANNEL_MATRIX_SPDIF
Address: A9h Type: R/W Bit 7 Bit 6 CM_SOURCE_SPDIF[2:0] Bit 5
Channel Matrix Configuration
Bit 4
Bit 3
Bit 2
Bit 1 CM_MATRIX_SPDIF[2:0]
Bit 0
CM_POSITION_SPDIF[1:0]
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STV82X8
Register List
Bit Name
CM_SOURCE_SPD IF[2:0] CM_POSITION_SP DIF[1:0] CM_MATRIX_SPDI F[2:0]
Reset
000 00 0000
Function
Select the source to copy on SPDIF channel. See table 7. Select the position for the SPDIF matrix. See block diagram. Select the matrixing for the SPDIF channels. See table 5.
Table 14: Channel Matrix Modes Parameter Coding (Bin)
000 001 010 011 100 101 110 111
Parameter Field Lebel
BYPASS LEFT ONLY RIGHT ONLY LEFT + RIGHT MIX SWAP -
Function
Bypass Stereo Signal Copy Left Signal On Both Channels Copy Right Signal On Both Channels Copy (Left + Right)/2 On Both Channels Swap Channel (Left = Right, Right = Left) Reserved Reserved Reserved
Table 15: Automatic Channel Matrix Modes Standard Detected by Autostandard MONO_SAP_CTRL_MATRIX reg 0x8A, bit[6] value = 0
Left Output Mono Stereo SAP Mono Signal Left Signal SAP Signal Right Output Mono Signal Right Signal SAP Signal
MONO_SAP_CTRL_MATRIX reg 0x8A, bit[6] value = 1
Left Output Mono Signal Left Signal Mono Signal Right Output Mono Signal Right Signal SAP Signal
Table 16: Channel Matrix Source Selection Parameter Coding (Bin)
000 001 010 011 100 101
Parameter Field Lebel
BYPASS LS Channels HP Channels C/Sub Channels Ls/Rs Channels -
Function
bypass stereo signal coming from Audiomatrix copy signal from LS channels copy signal from HP channels copy signal from C/Sub channels (ONLY AVAILABLE ON SPDIF CHANNEL MATRIX) copy signal from Ls/Rs channels (ONLY AVAILABLE ON SPDIF CHANNEL MATRIX) Reserved
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Register List
Table 16: Channel Matrix Source Selection (Continued) Parameter Coding (Bin)
110 111 -
STV82X8
Parameter Field Lebel
Reserved Reserved
Function
DEMOD_DC_LEVEL
Address: AAh Type: R Bit 7 Bit 6 Bit 5
DC Level on Demod FM Mono Input
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DEMOD_DC_LEVEL[7:0] (S)
Bit Name
DEMOD_DC_LEVE L[7:0]
Reset
(0000 0000)
Function
Display the amount of the DC component in the signal comming from the FM mono channel. This DC Level can be used to implement a Carrier Offset compensation.
12.14 Audio Processing
AV_DELAY_CONFIG
Address: ADh Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 Bit 0
AV Delay Configuration
DOLBY_DELA AV_DELAY_O Y_ON N
Bit Name
Bits[7:2] DOLBY_DELAY_O N AV_DELAY_ON
Reset
0000 00 Reserved
Function
0
Must be set to 1 to use the Center, Left Srnd and Right Srnd delays for ProLogic decoder multichannel output. Note: This value must be updated when AV_DELAY_ON = 0..
0
0: 1:
No AV delay AV delay is active
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STV82X8 AV_DELAY_TIME_LS
Address: AEh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Register List AV Delay LS Configuration
Bit 0
AV_DELAY_TIME_LS[7:0]
Bit Name
Reset
Set the delay time for LS channel.
Function
AV_DELAY_TIME_ LS[7:0]
0000 0000
0000 0000: 0000 0001: ... 1011 0001:
0 ms 0.66 ms 116.82 ms (max)
Note: this value must be updated when AV_DELAY_ON = 0..
AV_DELAY_TIME_HP
Address: AFh Type: R/W Bit 7 Bit 6 Bit 5
AV Delay HP Configuration
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
AV_DELAY_TIME_HP[7:0]
Bit Name
AV_DELAY_TIME_ HP[7:0]
Reset
Set the delay time for HP channel. 0000 0000 0000 0000: 0000 0001: ... 1011 0001: 0 ms 0.66 ms 116.82 ms (max)
Function
Note: this value must be updated when AV_DELAY_ON = 0..
Note:
The sum of AV_DELAY_TIME_LS and AV_DELAY_TIME_HP must not exceed: * 177 (116.82 ms) if DOLBY_DELAY_ON = 0 * 100 (66.66 ms) if DOLBY_DELAY_ON = 1
PRO_LOGIC2_CONTROL
Address: B0h Type: R/W Bit 7 PL2_LFE Bit 6 Bit 5
Dolby ProLogic 2 Mode Configuration
Bit 4
Bit 3
Bit 2 PL2_MODES[2:0]
Bit 1
Bit 0 PL2_ACTIVE
PL2_OUTPUT_DOWNMIX[2:0]
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Register List
STV82X8
Bit Name
PL2_LFE 0
Reset
0: 1: 000: 001: 010: 011: 000: 001: 010: 011: 0: 1: Reset the LFE channel Bypass the LFE channel not applicable not applicable not applicable 3/0 output mode (L,R,C) Pro Logic 1 Emulation Virtual Music Movie (standard) Dolby Prologic 2 is not active Dolby Prologic 2 is active
Function
PL2_OUTPUT_DO 000 WNMIX[2:0]
100: 101: 110: 111: 100: 101: 110: 111:
2/1 output mode (L,R,Ls - phantom) 3/1 output mode (L,R,C,Ls) 2/2 output mode (L,R,Ls,Rs - phantom) 3/2 output mode (L,R,C,Ls,Rs)
PL2_MODES[2:0]
000
Matrix Custom not applicable not applicable
PL2_ACTIVE
0
PRO_LOGIC2_CONFIG
Address: B1h Type: R/W Bit 7 0 Bit 6 0 Bit 5 0
Dolby ProLogic 2 Configuration
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PL2_SRND_FILTER[1:0]
PL2_RS_POL PL2_PANORA PL2_AUTOBA ARITY MA LANCE
Bit Name
Bits[7:6] PL2_SRND_FILTE R[1:0] PL2_RS_POLARIT Y PL2_PANORAMA PL2_AUTOBALAN CE
Reset
00 Reserved. 00: 01: 10: 11: 0: 1: 0: 1: 0: 1: Off Shelf 7-kHz LP not applicable Rs polarity normal Rs polarity inverted Panorama Off Panorama On Autobalance Off Autobalance On
Function
00
0 0 0
PRO_LOGIC2_DIMENSION
Address: B2h Type: R/W Bit 7 0 Bit 6 Bit 5 PL2_C_WIDTH
Dolby ProLogic 2 Dimension
Bit 4
Bit 3 0
Bit 2
Bit 1 PL2_DIMENSION
Bit 0
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STV82X8
Register List
Bit Name
Bit 7 0
Reset
Reserved. ProLogic 2 center width:
Function
PL2_C_WIDTH[2:0] 000
000: 001: 010: 011:
0, no spread 20 28 36
100: 101: 110: 111:
54 62 69 90, phantom
Bit 3
0
Reserved. ProLogic 2 dimension:
PL2_DIMENSION [ 000 2:0]
000: 001: 010: 011:
-3, most surround -2 -1 0, neutral
100: 101: 110: 111:
1 2 3, most center not used
PRO_LOGIC2_LEVEL
Address: B3h Type: R/W Bit 7 Bit 6 Bit 5
Dolby ProLogic 2 Input Level
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PL2_LEVEL
Bit Name
Reset
Input Gain attenuation:
Function
PL2_LEVEL[7:0]
0000000 0000 0000: 0000 0001: 0 ... 1111 1111:
0 dB -0.5 dB -127.5 dB
NOISE_GENERATOR
Address: B4h Type: R/W Bit 7 Bit 6 Bit 5
Pink Noise Generator
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 NOISE_ON
10_DB_ATTEN SRIGHT_NOIS SLEFT_NOISE SUB_NOISE UATE E
CENTER_NOI RIGHT_NOISE LEFT_NOISE SE
Bit Name
10_DB_ATTENUAT 0 E SRIGHT_NOISE SLEFT_NOISE SUB_NOISE 0 0 0
Reset
0: 1: 1: 1: 1: noise is output with full range noise is output with a 10dB attenuation
Function
Generates noise on LS right surround output Generates noise on LS left surround output Generates noise on LS subwoofer output
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Register List
STV82X8
Bit Name
CENTER_NOISE RIGHT_NOISE LEFT_NOISE NOISE_ON 0 0 0 0
Reset
1: 1: 1: 0: 1: Generates noise on LS center output Generates noise on LS right output Generates noise on LS left output Noise Generation not active Noise Generation active
Function
PCM_SRND_DELAY
Address: B5h Type: R/W Bit 7 0 Bit 6 0 Bit 5 0
Dolby Surround Delay
Bit 4
Bit 3
Bit 2 DOLBY_DELAY_SRND[4:0]
Bit 1
Bit 0
Bit Name
Bits[7:5] DOLBY_DELAY_S RND[4:0]
Reset
000 00000 Reserved. Surround Channel Delay Range: 0 to 30 (in ms)
Function
Note:
To use this feature, set the DOLBY_DELAY_ON bit to 1 in register AV_DELAY_CONFIG (ADh).
PCM_CENTER_DELAY
Address: B6h Type: R/W Bit 7 0 Bit 6 0 Bit 5 0
Dolby Center Delay Register
Bit 4 0
Bit 3
Bit 2
Bit 1
Bit 0
DOLBY_DELAY_CENTER[3:0]
Bit Name
Bits[7:4] DOLBY_DELAY_C ENTER[3:0]
Reset
0000 0000 Reserved. Center Channel Delay Range: 0 to 10 (in ms)
Function
Note:
To use this feature, set the DOLBY_DELAY_ON bit to 1 in register AV_DELAY_CONFIG (ADh).
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STV82X8 TRUSRND_CONTROL
Address: B7h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Register List SRS TruSurround Control
Bit 0
DIALOG_CLA HEADPHONE RITY_ON _ON
TRUSRND_INPUT_ MODE[3:0]
TRUSRND_BY TRUSRND_O PASS N
Bit Name
DIALOG_CLARITY _ON
Reset
0: 1: Dialog Clarity OFF Dialog Clarity ON
Function
0
Note: The Dialog Clarity Level is set in register 0xB8: TRUSRND_DC_ELEVATION Process the sound espacialy for Headphone. This option must be selected only if the TruSurround sound is redirected to the headphone output thanks to the HP channel matrix. 0: 1: Standard mode for Loudspeaker output Headphone mode for Headphone output only Mono on Center channel Mono on Left channel L/R stereo (SRS mode) L/R/S (SRS mode, Prologic 1 Process) L/R/Ls/Rs (SRS mode) L/R/C (TruSurround mode) L/R/C/S (TruSurround mode, Prologic 1 Process) L/R/C/Ls/Rs (TruSurround mode) Lt/Rt (TruSurround mode) L/R/C/Ls/Rs (SRS mode, BS Digital Broadcast) L/R/C/Ls/Rs (TruSurround, Prologic 2 Music mode)
HEADPHONE_ON
0
TRUSRND_INPUT_ MODE[3:0]
0000
0000: 0001: 0010: 0011: 0100: 0101: 0110: 0111: 1000: 1001: 1010:
TRUSRND_BYPAS S
Bypass the TruSurround effect by applying a simple donwmix on input channels. 0 0: 1: 0: 1: TruSurround mode Bypass mode (downmix to 2 channels) TruSurround OFF TruSurround ON
TRUSRND_ON
0
TRUSRND_DC_ELEVATION
Address: B8h Type: R/W Bit 7 Bit 6 Bit 5
Set Dialog Clarity Level
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TRUSRND_DC_ELEVATION[7:0]
Bit Name
Reset
Dialog Clarity Elevation: 0000 0000: 0000 0001: ... 1111 1111: 0 dB -0.5 dB -127.5 dB
Function
TRUSRND_DC_EL 0000 EVATION[7:0] 1100
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Register List TRUSRND_INPUT_GAIN
Address: B9h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
STV82X8 Input Gain for TruSurround
Bit 0
TRUSRND_INPUT_GAIN[7:0]
Bit Name
Reset
Input Gain attenuation: 0000 0000: 0 dB 0000 0001: -0.5 dB ... 1111 1111: -127.5 dB
Function
TRUSRND_INPUT_ 0000 GAIN[7:0] 0000
TRUBASS_LS_CONTROL
Address: BAh Type: R/W Bit 7 0 Bit 6 0 Bit 5 0
SRS TruBass for LS Configuration
Bit 4 0
Bit 3
Bit 2 TRUBASS_LS_SIZE[2:0]
Bit 1
Bit 0 TRUBASS_LS _ON
Bit Name
Bits[7:3] TRUBASS_LS_SIZ E[2:0]
Reset
0000 Reserved. 000: 001: 010: 011: 0: 1: LF response at 40 Hz LF response at 60 Hz LF response at 100 Hz LF response at 150 Hz LS TruBass OFF LS TruBass ON 100: 101: 110: 111:
Function
011
LF response at 200 Hz LF response at 250 Hz LF response at 300 Hz LF response at 400 Hz
TRUBASS_LS_ON
0
TRUBASS_LS_LEVEL
Address: BBh Type: R/W Bit 7 Bit 6 Bit 5
SRS TruBass for LS Level
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TRUBASS_LS_LEVEL[7:0]
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STV82X8
Register List
Bit Name
Reset
Function
Define the amount of SRS TruBass effect for LS outputs: 0000 0000: 0dB 0000 0001: -0.5dB ... 1111 1111: -127.5dB
TRUBASS_LS_LEV 0000 EL[7:0] 1001
TRUBASS_HP_CONTROL
Address: BCh Type: R/W Bit 7 SRS_TSXT_G AIN_ON Bit 6 0 Bit 5 0
SRS TruBass for HP Configuration
Bit 4 0
Bit 3
Bit 2 TRUBASS_HP_SIZE[2:0]
Bit 1
Bit 0 TRUBASS_HP _ON
Bit Name
SRS_TSXT_GAIN_ 0 ON
Reset
Function
Apply the TruSurround Gain (register 0xB9) to the TruBass input block. This gain must be applied only if the TruSurround signal have been redirected to the TruBass HP thanks to the HP Channel Matrix. 0: TSXT input gain is not applied 1: TSXT input gain is applied. (this configuration must be used if the LS signal processed with TSXT is redirected to the HP channel)
Bits[6:3] TRUBASS_HP_SIZ E[2:0]
000
Reserved. 000: 001: 010: 011: 0: 1: LF response at 40 Hz LF response at 60 Hz LF response at 100 Hz LF response at 150 Hz HP TruBass OFF HP TruBass ON 100: 101: 110: 111: LF response at 200 Hz LF response at 250 Hz LF response at 300 Hz LF response at 400 Hz
011
TRUBASS_HP_ON
0
TRUBASS_HP_LEVEL
Address: BDh Type: R/W Bit 7 Bit 6 Bit 5
SRS TruBass for HP Level
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TRUBASS_HP_LEVEL[7:0]
Bit Name
TRUBASS_HP_LE VEL[7:0]
Reset
0000 1001
Function
Define the amount of SRS TruBass effect for HP outputs: 0000 0000: 0dB 0000 0001: -0.5dB ... 1111 1111: -127.5dB
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Register List SVC_LS_CONTROL
Address: BEh Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 Bit 2 Bit 1 SVC_LS_AMP
STV82X8 Smart Volume Control for LS
Bit 0 SVC_LS_ON
SVC_LS_INPUT[1:0]
Bit Name
Bits[7:4] SVC_LS_INPUT[ 1:0]
Reset
0000 Reserved.
Function
Select input for peak detection in multichannel mode: 00 00: 01: 10: 11: 0: 1: 0: 1: Left/Right Center Left/Right/Center Not Used 0 dB amplification in auto-mode +6 dB amplification in auto-mode Manual mode(simple prescaler) Automatic mode
SVC_LS_AMP SVC_LS_ON
1 0
SVC_LS_TIME_TH
Address: BFh Type: R/W Bit 7 Bit 6 SVC_LS_TIME[2:0] Bit 5
Smart Volume Control Parameters for LS
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SVC_LS_THRESHOLD[4:0]
Bit Name
Reset
Function
Time Constant for Amplification (6-dB gain step) in Automatic mode:
SVC_LS_TIME[2:0] 100
000: 001: 010: 011:
30 ms 200 ms 500 ms 1s
100: 101: 110: 111:
16 s 32 s 64 s 128 s
SVC_LS_THRESH 11000 OLD[4:0]
See tables 8 and 9
Table 17: Gain (Threshold Field) Values in Manual mode Manual Mode
00101 00100 00011 00010
Gain (dB)
+15.5 +12 +9.5 +6
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STV82X8
Table 17: Gain (Threshold Field) Values in Manual mode (Continued) Manual Mode
00001 00000 11111 11110 11101 11100 11011 11010 11001 11000 10111 10110
Register List
Gain (dB)
+3.5 0 -2.5 -6 -8.5 -12 -14.5 -18 -20.5 -24 -26.5 -30
Table 18: Threshold values in Automatic mode Automatic Mode
11111 11110 11101 11100 11011 11010 11001 11000 10111 10110
Threshold (dB)
-2.5 -6 -8.5 -12 -14.5 -18 -20.5 -24 -26.5 -30
SVC_LS_GAIN
Address: C0h Type: R/W Bit 7 0 Bit 6 0 Bit 5
Make-up Gain for SVC LS
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SVC_LS_GAIN[5:0]
Bit Name
Bits[7:6]
Reset
00 Reserved.
Function
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Register List
STV82X8
Bit Name
Reset
Function
SVC_LS_GAIN[5:0]
Set "make-up" gain applied at SVC LS output: 000000: +0 dB 000001: +0.5 dB 000000 ... 101110: +23 dB 101111: +23.5 dB 110000: +24 dB
SVC_HP_CONTROL
Address: C1h Type: R/W Bit 7 0 Bit 6 0 Bit 5 0
Smart Volume Control for HP
Bit 4 0
Bit 3 0
Bit 2 0
Bit 1
Bit 0
SVC_HP_AMP SVC_HP_ON
Bit Name
Bits[7:2] SVC_HP_AMP SVC_HP_ON
Reset
0000 00 1 0 Reserved. 0: 0 dB amplification in auto-mode 1: +6 dB amplification in auto-mode 0: Manual mode (simple prescaler) 1: Automatic mode
Function
SVC_HP_TIME_TH
Address: C2h Type: R/W Bit 7 Bit 6 SVC_HP_TIME[2:0] Bit 5
Smart Volume Control Parameters for HP
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SVC_HP_THRESHOLD[4:0]
Bit Name
SVC_HP_TIME[2:0]
Reset
Function
Time Constant for Amplification (6-dB gain step) in Automatic mode:
100
000: 001: 010: 011:
30 ms 200 ms 500 ms 1s
100: 101: 110: 111:
16 s 32 s 64 s 128 s
SVC_HP_THRESH 11000 OLD[4:0]
See tables 8 and 9
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STV82X8 SVC_HP_GAIN
Address: C3h Type: R/W Bit 7 0 Bit 6 0 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Register List Make-up Gain for SVC HP
Bit 0
SVC_HP_GAIN[5:0]
Bit Name
Bits[7:6]
Reset
00 Reserved.
Function
Set "make-up" gain applied at SVC HP output: 000000: +0 dB 000001: +0.5 dB SVC_HP_GAIN[5:0] 000000 ... 101110: +23 dB 101111: +23.5 dB 110000: +24 dB
WIDESRND_CONTROL
Address: C4h Type: R/W Bit 7 0 Bit 6 0 Bit 5 0
ST Wide Surround Control
Bit 4 0
Bit 3 0
Bit 2
Bit 1
Bit 0
WIDESRND_S WIDESRND_ WIDESRND_O TEREO MODE N
Bit Name
Bits[7:3]
Reset
00000 Reserved. ST Wide Surround Sound Stereo Mode 0: 1:
Function
WIDESRND_STER 0 EO
ST Wide Surround Sound in Mono mode (Default) ST Wide Surround Sound in Stereo mode
WIDESRND_MODE 0
ST Wide Surround Sound Stereo Mode 0: 1: Movie Mode Music Lode
WIDESRND_ON
0
ST Wide Surround Sound Enable 0: 1: ST Wide Surround Sound is disabled ST Wide Surround Sound is enabled
WIDESRND_FREQ
Address: C5h Type: R/W Bit 7 0 Bit 6 0 Bit 5
ST Wide Surround Sound Frequency
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WIDESRND_BASS[1:0]
WIDESRND_MEDIUM[1:0]
WIDESRND_TREBLE[1:0]
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Register List
STV82X8
Bit Name
Bits[7:6]
Reset
00 Reserved.
Function
WIDESRND_BASS[ 01 1:0] WIDESRND_MEDI 01 UM[1:0] WIDESRND_TREB 01 LE[1:0]
Defines the bass frequency effect for ST Wide Surround Sound. Programmable values are listed in Table 10. Defines the medium frequency effect for ST Wide Surround Sound in Movie or Mono mode (no effect in Music mode). Programmable values are listed in Table 10. Defines the treble frequency effect for ST Wide Surround Sound in Movie or Mono mode (no effect in Music mode). Programmable values are listed in Table 10.
Table 19: Phase Shifter Center Frequencies Phase Shifter Center Frequency BASS_FREQ[1:0]
00 01 (Default) 10 11 40 Hz 90 Hz 120 Hz 160 Hz
MEDIUM_FREQ[1:0]
202 Hz 416 Hz 500 Hz 588 Hz
TREBLE_FREQ[1:0]
2 kHz 4 kHz 5 kHz 6 kHz
WIDESRND_LEVEL
Address: C6h Type: R/W Bit 7 Bit 6 Bit 5
ST Wide Surround Gain
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WIDESRND_GAIN[7:0]
Bit Name
Reset
Function
Defines the ST Wide Surround Sound component gain in linear scale. Level (%) 1000 0000 (Default) 0111 1111 0111 1110 0111 1101 ........ 100% 99.2% 98.4% 97.6% 0000 0100 0000 0011 0000 0010 0000 0001 0000 0000 Level (%) 3.1% 2.3% 1.6% 0.8% 0%
WIDESRND_GAIN[ 10000000 7:0]
OMNISURROUND_CONTROL
Address: C7h Type: R/W Bit 7 Bit 6 Bit 5 SRND_PHASE _INV Bit 4
ST Omnisurround Configuration
Bit 3
Bit 2
Bit 1
Bit 0 OMNISRND_O N
ST_VOICE[1:0]
OMNISRND_INPUT_MODE[3:0]
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STV82X8
Register List
Bit Name
Reset
00: 01: 10: 11: OFF Low Mid High
Function
ST_VOICE[1:0]
00
SRND_PHASE_INV 0
Invert Right Surround phase in 2_2 or 3_2 input mode: 0: 1: Right Surround phase not inverted Right Surround phase invertedl Mono on center channel Mono on left channel L/R stereo L/R/S L/R/Ls/Rs 0101: L/R/C 0110: L/R/C/S 0111: L/R/C/Ls/Rs 1000: Lt/Rt (Passive matrix)
OMNISRND_INPUT _ MODE[3:0] 0000
0000: 0001: 0010: 0011: 0100: 0: 1:
OMNISRND_ON
0
OmniSurround OFF OmniSurround ON
DYNAMIC_BASS_LS
Address: C8h Type: R/W Bit 7 Bit 6 Bit 5 LS_BASS_LEVEL[4:0]
ST Dynamic Bass for LS
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 LS_DYN_BAS S_ON
LS_BASS_FREQ[1:0]
Bit Name
LS_BASS_LEVEL [ 4:0]
Reset
ST Dynamic Bass output gain: 00000: +0dB 00001: +0.5dB ... 11101: +14.5dB 11110: +15dB 11111: +15.5dB 00: 100-Hz Cut-Off frequency 01: 150-Hz Cut-Off frequency 0: 1: ST Dynamic Bass OFF ST Dynamic Bass ON
Function
00000
LS_BASS_FREQ [ 1:0] LS_DYN_BASS_O N
00 0
10: 200-Hz Cut-Off frequency 11: 250-Hz Cut-Off frequency
DYNAMIC_BASS_HP
Address: C9h Type: R/W Bit 7 Bit 6 Bit 5 HP_BASS_LEVEL[4:0]
ST Dynamic Bass for HP
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 HP_DYN_BAS S_ON
HP_BASS_FREQ[1:0]
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Register List
STV82X8
Bit Name
HP_BASS_LEVEL[ 4:0]
Reset
ST Dynamic Bass output gain: 00000: +0dB 00001: +0.5dB ... 11101: +14.5dB 11110: +15dB 11111: +15.5dB 00: 100-Hz Cut-Off frequency 01: 150-Hz Cut-Off frequency 0: 1: ST Dynamic Bass OFF ST Dynamic Bass ON
Function
00000
HP_BASS_FREQ[ 1:0]
00
10: 200-Hz Cut-Off frequency 11: 250-Hz Cut-Off frequency
HP_DYN_BASS_O 0 N
BASS_ENHANCE_LS
Address: CAh Type: R/W Bit 7 0 Bit 6 0 Bit 5 LS_BASS_EN HANCE_HP_F ILTER
ST Bass Enhancer for LS
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LS_BASS_ENHANCE_SCALE[2:0]
LS_BASS_EN LS_BASS_EN HANCE_CUT HANCE_ON OFF
Bit Name
Bits[7:6] LS_BASS_ENHAN CE_HP_FILTER
Reset
00 Reserved.
Function
0
Add an High Pass Filter in order to reduce the lower bass content in the signal in order to reduce the constraint on small speakers. 0: 1: No High Pass Filter. To be used on wide band speakers High Pass Filter. To be used on narrow band speakers.
LS_BASS_ENHAN CE_SCALE[2:0]
Set the amount of bass generated by the processing: 000 000: ... 111: Light Bass Content Stong Bass Content
LS_BASS_ENHAN 0 CE_CUTOFF LS_DYN_BASS_O N
Define the corner frequency for the bass generation: 0: 1: 0: 1: Cuttoff Frequency = 80 Hz Cutoff Frequency = 120 Hz ST Bass Enhancer OFF ST Bass Enhancer ON
0
EQ_BT_CTRL
Address: CCh Type: R/W Bit 7 0 Bit 6 0 Bit 5 0
Loudspeakers Equalizer Control
Bit 4 0
Bit 3 0
Bit 2 HP_BT_ON
Bit 1 LS_EQ_BT_S W
Bit 0 LS_EQ_ON
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STV82X8
Register List
Bit Name
Bits[7:3] HP_BT_ON
Reset
00000 0 Reserved. Bass-Treble for HP Enable 0: 1: Bass-Treble is disabled Bass-Treble is enabled
Function
LS_EQ_BT_SW
0
5-Band Equalizer or Bass-Teble for LS selection 0: 1: 5-Band Equalizer is selected for Loudspeakers. Bass-Treble is selected for Loudspeakers.
LS_EQ_ON
1
5-Band Equalizer/Bass-Treble for LS Enable 0: 1: 5-Band Equalizer/Bass-Treble is disabled 5-Band Equalizer/Bass-Treble is enabled
LS_EQ_BANDX
Address: CDh to D1h Type: R/W Bit 7 Bit 6 Bit 5
Loudspeakers Equalizer Gain for BandX
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
EQ_BANDX[7:0]
Bit Name
EQ_BANDX[7:0]
Reset
0000 0000
Function
BandX gain adjustment within a range from -12 dB to +12 dB in steps of 0.25 dB. Band1: 100 Hz, Band2: 330 Hz, Band3: 1 kHz, Band4: 3.3 kHz, Band5: 10 kHz.
Table 20: Loudspeakers Equalizer/Bass-Treble Gain Values (and Headphone Bass-Treble Gain Values) Value
00110000 00101111 00101110 ................ 00000000 (Default) ................ 10101110 10101111 10110000
Gain G (dB)
+12 +11.75 +11.50 ..... 0 ..... -11.50 -11.75 -12
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Register List LS_BASS_GAIN
Address: D2h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
STV82X8 Loudspeakers Bass Gain Register
Bit 0
LS_BASS[7:0]
Bit Name
LS_BASS[7:0]
Reset
0000 0000
Function
Gain Tuning of Loudspeakers Bass Frequency Gain may be programmed within a range between +12 dB and -12 dB in steps of 0.25 dB. Programmable values are listed in Table 11.
LS_TREBLE_GAIN
Address: D3h Type: R/W Bit 7 Bit 6 Bit 5
Loudspeakers Treble Gain Register
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LS_TREBLE
Bit Name
LS_TREBLE[7:0]
Reset
0000 0000
Function
Gain Tuning of Loudspeakers Treble Frequency Gain may be programmed within a range between +12 dB and -12 dB in steps of 0.25 dB. Programmable values are listed in Table 11.
HP_BASS_GAIN
Address: D4h Type: R/W Bit 7 Bit 6 Bit 5
Headphone Bass Gain
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
HP_BASS[7:0]
Bit Name
HP_BASS[7:0]
Reset
Function
0000000 Gain Tuning of Headphone Bass Frequency 0 Gain may be programmed within a range between +12 dB and -12 dB in steps of 0.25 dB. Programmable values are listed in Table 11.
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STV82X8 HP_TREBLE_GAIN
Address: D5h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Register List Headphone Treble Gain
Bit 0
HP_TREBLE
Bit Name
HP_TREBLE[7:0]
Reset
0000 0000
Function
Gain Tuning of Headphone Treble Frequency Gain may be programmed within a range between +12 dB and -12 dB in steps of 0.25 dB. Programmable values are listed in Table 11.
OUTPUT_BASS_MNGT
Address: D4h Type: R/W Bit 7 BASS_MANA GE_ON Bit 6 ST_LFE_ADD Bit 5
Bass Redirection
Bit 4
Bit 3 GAIN_SWITC H
Bit 2
Bit 1 OCFG_NUM[2:0]
Bit 0
DOLBY_PROL SUB_ACTIVE OGIC
Bit Name
BASS_MANAGE_O N ST_LFE_ADD
Reset
0 0 0: 1: BassManagement disabled BassManagement enabled
Function
Add the signal comming from the LFE input (MULTI_I2S mode only) to the calculated Subwoofer signal: 0: 1: No LFE channel to add Add LFE signal to the Subwoofer computed signal
DOLBY_PROLOGI C
0
If the BassManagement is used with Dolby Prologic decoder, the surround channels must not be added to generate the Subwoofer channel: 0: 1: Standard configuration (Dolby Digital compliant), surround channels are used to generate the Subwoofer channel. Dolby Prologic configuration, surround channels are not used to generate the Subwoofer channel.
SUB_ACTIVE
0
In some configurations the Subwoofer signal can be redirected to L/R channels if there is no Subwoofer output:. 0: 1: No Subwoofer output, the Sub signal is added to L/R channels Subwoofer signal is outputed on Subwoofer output.
GAIN_SWITCH
0
Gain Switch available in some configurations: 0: 1: Level Adjustment ON Level Adjustment OFF
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Register List
STV82X8
Bit Name
OCFG_NUM[2:0]
Reset
000 Select Bass Management configuration: 000: 001: 010: 011: 100: 101: 110: 111:
Function
Output Configuration 0 Output Configuration 1 Output Configuration 2 Output Configuration 3 Output Configuration 4 (Simplified Configuration) Output Configuration 5 (Stereo Full Bandwith Speakers) Output Configuration 6 (Stereo Narrow Bandwith Speakers) Not Used
LS_LOUDNESS
Address: D7h Type: R/W Bit 7 0 Bit 6 Bit 5
Loudness Configuration for LS
Bit 4
Bit 3
Bit 2 LS_LOUD_GAIN_HR[2:0]
Bit 1
Bit 0 LS_LOUD_ON
LS_LOUD_THRESHOLD[2:0]
Bit Name
Bit 7 LS_LOUD_THRES HOLD[2:0]
Reset
0 000 Reserved.
Function
Define the volume threshold level since which loudness effect is applied: 000: 001: 010: 011: 0 dB -6 dB -12 dB -18 dB 100: 101: 110: 111: -24 dB -32 dB -36 dB -42 dB
LS_LOUD_GAIN_H R[2:0]
010
Define the amount of Treble added by loudness effect: 000: 001: 010: 011: 0 dB 3 dB 6 dB 9 dB 100: 101: 110: 111: 12 dB 15 dB 18 dB Not Used
LS_LOUD_ON
0
0: 1:
Loudness is not active on LS output Loudness is active on LS output
HP_LOUDNESS
Address: D8h Type: R/W Bit 7 0 Bit 6 Bit 5
Loudness Configuration for HP
Bit 4
Bit 3
Bit 2 HP_LOUD_GAIN_HR[2:0]
Bit 1
Bit 0 HP_LOUD_ON
HP_LOUD_THRESHOLD[2:0]
Bit Name
Bit 7
Reset
0 Reserved.
Function
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STV82X8
Register List
Bit Name
HP_LOUD_THRES HOLD[2:0]
Reset
000
Function
Define the volume threshold level since which loudness effect is applied : 000: 001: 010: 011: 0 dB -6 dB -12 dB -18 dB 100: 101: 110: 111: -24 dB -32 dB -36 dB -42 dB
HP_LOUD_GAIN_H R[2:0]
010
Define the amount of Treble added by loudness effect: 000: 001: 010: 011: 0 dB 3 dB 6 dB 9 dB 100: 101: 110: 111: 12 dB 15 dB 18 dB not used
HP_LOUD_ON
0
0: 1:
Loudness is not active on HP output Loudness is active on HP output
VOLUME_MODES
Address: D9h Type: R/W Bit 7 Bit 6 Bit 5 0
Set the Volume Modes
Bit 4 SCART2_ VOLUME_ MODE
Bit 3 SCART1_ VOLUME_ MODE
Bit 2 HP_ VOLUME_ MODE
Bit 1 SRND_ VOLUME_ MODE
Bit 0 LS_ VOLUME_ MODE
ANTICLIP_HP ANTICLIP_LS _VOL_CLAMP _VOL_CLAMP
Bit Name
ANTICLIP_HP_VOL _CLAMP
Reset
1
Function
The output level is clamped depending on the HP Bass-Treble value to avoid any possible signal clipping on HP output. 0: Volume clamp on HP output is not active 1: Volume clamp on HP output is active
ANTICLIP_LS_VOL _CLAMP
1
The output level is clamped depending on the LS Equalizer or LS Bass-Treble value to avoid any possible signal clipping on LS output. 0: Volume clamp on LS output is not active 1: Volume clamp on LS output is active
Bits[5] SCART2_VOLUME _MODE
0 1
Reserved. Volume mode for SCART2 output: 0: 1: Independant Differential
SCART1_VOLUME _MODE
1
Volume mode for SCART1 output: 0: 1: Independant Differential
HP_VOLUME_ MODE
1
Volume mode for Headphone output: 0: 1: Independant Differential
SRND_VOLUME_ MODE
1
Volume mode for Surround output: 0: 1: Independant Differential
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Register List
STV82X8
Bit Name
LS_VOLUME_ MODE
Reset
1 Volume mode for LS output: 0: 1: Independant Differential
Function
LS_L_VOLUME_MSB
Address: DAh Type: R/W Bit 7 Bit 6 Bit 5
Loudspeaker Left Volume MSB
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LS_L_VOLUME_MSB[7:0]
Bit Name
LS_L_VOLUME_M SB[7:0]
Reset
1001 1000
Function
8 MSBs of the 10-bit Left Loudspeaker Volume
LS_L_VOLUME_LSB
Address: DBh Type: R/W Bit 7 0 Bit 6 0 Bit 5 0
Loudspeaker Left Volume LSB
Bit 4 0
Bit 3 0
Bit 2 0
Bit 1
Bit 0
LS_L_VOLUME_LSB[1:0]
Bit Name
Bits[7:2] LS_L_VOLUME_LS B[1:0]
Reset
000000 Reserved. 00
Function
2 LSBs of the 10-bit Left Loudspeaker Volume
LS_R_VOLUME_MSB
Address: DCh Type: R/W Bit 7 Bit 6 Bit 5
Loudspeaker Right Volume MSB
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LS_R_VOLUME_MSB[7:0]
Bit Name
LS_R_VOLUME_M SB[7:0]
Reset
0000 0000
Function
8 MSBs of the 10-bit Right Loudspeaker Volume
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STV82X8 LS_R_VOLUME_LSB
Address: DDh Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1
Register List Loudspeaker Right Volume LSB
Bit 0
LS_R_VOLUME_LSB[1:0]
Bit Name
Bits[7:2] LS_R_VOLUME_L SB[1:0]
Reset
000000 Reserved. 00
Function
2 LSBs of the 10-bit Right Loudspeaker Volume
LS_C_VOLUME_MSB
Address: DEh Type: R/W Bit 7 Bit 6 Bit 5
Loudspeaker Center Volume MSB
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LS_C_VOLUME_MSB[7:0]
Bit Name
LS_C_VOLUME_M SB[7:0]
Reset
1001 1000
Function
8 MSBs of the 10-bit Center Loudspeaker Volume
LS_C_VOLUME_LSB
Address: DFh Type: R/W Bit 7 0 Bit 6 0 Bit 5 0
Loudspeaker Center Volume LSB
Bit 4 0
Bit 3 0
Bit 2 0
Bit 1
Bit 0
LS_C_VOLUME_LSB[1:0]
Bit Name
Bits[7:2] LS_C_VOLUME_L SB[1:0]
Reset
0000 00 Reserved. 00
Function
2 LSBs of the 10-bit Center Loudspeaker Volume
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Register List LS_SUB_VOLUME_MSB
Address: E0h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
STV82X8 Loudspeaker Subwoofer Volume MSB
Bit 0
LS_SUB_VOLUME_MSB[7:0]
Bit Name
LS_SUB_VOLUME _MSB[7:0]
Reset
1001 1000
Function
8 MSBs of the 10-bit Subwoofer Loudspeaker Volume
LS_SUB_VOLUME_LSB
Address: E1h Type: R/W Bit 7 0 Bit 6 0 Bit 5 0
Loudspeaker Subwoofer Volume LSB
Bit 4 0
Bit 3 0
Bit 2 0
Bit 1
Bit 0
LS_SUB_VOLUME_LSB[1:0]
Bit Name
Bits[7:2] LS_SUB_VOLUME _LSB[1:0]
Reset
000000 Reserved. 00
Function
2 LSBs of the 10-bit Subwoofer Loudspeaker Volume
LS_SL_VOLUME_MSB
Address: E2h Type: R/W Bit 7 Bit 6 Bit 5
Loudspeaker Left Surround Volume MSB
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LS_SL_VOLUME_MSB[7:0]
Bit Name
LS_SL_VOLUME_ MSB[7:0]
Reset
1001 1000
Function
8 MSBs of the 10-bit Left Surround Loudspeaker Volume
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STV82X8 LS_SL_VOLUME_LSB
Address: E3h Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1
Register List Loudspeaker Surround Left Volume LSB
Bit 0
LS_SL_VOLUME_LSB[1:0]
Bit Name
Bits[7:2] LS_SL_VOLUME_L SB[1:0]
Reset
000000 Reserved. 00
Function
2 LSBs of the 10-bit Left Surround Loudspeaker Volume
LS_SR_VOLUME_MSB
Address: E4h Type: R/W Bit 7 Bit 6 Bit 5
Louspeaker Surround Right Volume MSB
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LS_SR_VOLUME_MSB[7:0]
Bit Name
LS_SR_VOLUME_ MSB[7:0]
Reset
0000 0000
Function
8 MSBs of the 10-bit Right Surround Loudspeaker Volume
LS_SR_VOLUME_LSB
Address: E5h Type: R/W Bit 7 0 Bit 6 0 Bit 5 0
Loudspeaker Surround Right Volume LSB
Bit 4 0
Bit 3 0
Bit 2 0
Bit 1
Bit 0
LS_SR_VOLUME_LSB[1:0]
Bit Name
Bits[7:2] LS_SR_VOLUME_ LSB[1:0]
Reset
000000 Reserved. 00
Function
2 LSBs of the 10-bit Right Surround Loudspeaker Volume
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Register List LS_MASTER_VOLUME_MSB
Address: E6h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
STV82X8 Loudspeaker Master Volume MSB
Bit 0
LS_MASTER_VOLUME_MSB[7:0]
Bit Name
LS_MASTER_ VOLUME_MSB[7:0]
Reset
1110 1000
Function
8 MSBs of the 10-bit Master Loudspeaker Volume
LS_MASTER_VOLUME_LSB
Address: E7h Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0
Loudspeaker Master Volume LSB
Bit 3 0
Bit 2 0
Bit 1
Bit 0
LS_MASTER_VOLUME_LSB[ 1:0]
Bit Name
Bits[7:2] LS_MASTER_VOL UME_LSB[1:0]
Reset
000000 Reserved. 00
Function
2 LSBs of the 10-bit Master Loudspeaker Volume
HP_L_VOLUME_MSB
Address: E8h Type: R/W Bit 7 Bit 6 Bit 5
Headphone Left Volume MSB
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
HP_L_VOLUME_MSB[7:0]
Bit Name
HP_L_VOLUME_M SB[7:0]
Reset
1001 1000
Function
8 MSBs of the 10-bit Left Headphone Volume
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STV82X8 HP_L_VOLUME_LSB
Address: E9h Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1
Register List Headphone Left Volume LSB
Bit 0
HP_L_VOLUME_LSB[1:0]
Bit Name
Bits[7:2] HP_L_VOLUME_L SB[1:0]
Reset
000000 Reserved. 00
Function
2 LSBs of the 10-bit Left Headphone Volume
HP_R_VOLUME_MSB
Address: EAh Type: R/W Bit 7 Bit 6 Bit 5
Headphone Right Volume MSB
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
HP_R_VOLUME_MSB[7:0]
Bit Name
HP_R_VOLUME_ MSB[7:0]
Reset
Function
0000000 8 MSBs of the 10-bit Right Headphone Volume 0
HP_R_VOLUME_LSB
Address: EBh Type: R/W Bit 7 0 Bit 6 0 Bit 5 0
Headphone Right Volume LSB
Bit 4 0
Bit 3 0
Bit 2 0
Bit 1
Bit 0
HP_R_VOLUME_LSB[1:0]
Bit Name
Bits[7:2] HP_R_VOLUME_L SB[1:0]
Reset
000000 Reserved. 00
Function
2 LSBs of the 10-bit Right Headphone Volume
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Register List AUX_VOLUME_INDEX
Address: ECh Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1
STV82X8 Select the AUX to apply Volume
Bit 0
AUX_VOLUME_SELECT[1:0]
Bit Name
Bits[7:2] AUX_VOLUME_SE LECT[1:0]
Reset
000000 Reserved. 00
Function
Select the output on which the AUX_VOLUME values will be applied: 00: No volume applied (mandatory step to change selection from 01 to 10) 01: Volume applied to SCART1 output 10: Volume applied to SCART2 output 11: Not used
AUX_L_VOLUME_MSB
Address: EDh Type: R/W Bit 7 Bit 6 Bit 5
Auxiliary Left Volume MSB
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
AUX_L_VOLUME_MSB[7:0]
Bit Name
AUX_L_VOLUME_ MSB[7:0]
Reset
1001 1000 8 MSBs of the 10-bit Left Auxiliary Volume
Function
AUX_L_VOLUME_LSB
Address: EEh Type: R/W Bit 7 0 Bit 6 0 Bit 5 0
Auxiliary Left Volume LSB
Bit 4 0
Bit 3 0
Bit 2 0
Bit 1
Bit 0
AUX_L_VOLUME_LSB[1:0]
Bit Name
Bits[7:2] AUX_L_VOLUME_L SB[1:0]
Reset
000000 Reserved. 00 2 LSBs of the 10-bit Left Auxiliary Volume
Function
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STV82X8 AUX_R_VOLUME_MSB
Address: EFh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Register List Auxiliary Right Volume MSB
Bit 0
AUX_R_VOLUME_MSB[7:0]
Bit Name
AUX_R_VOLUME_ MSB[7:0]
Reset
0000 0000 8 MSBs of the 10-bit Right Auxiliary Volume
Function
AUX_R_VOLUME_LSB
Address: F0h Type: R/W Bit 7 0 Bit 6 0 Bit 5 0
Auxiliary Right Volume LSB
Bit 4 0
Bit 3 0
Bit 2 0
Bit 1
Bit 0
AUX_R_VOLUME_LSB[1:0]
Bit Name
Bits[7:2] AUX_R_VOLUME_ LSB[1:0]
Reset
000000 Reserved. 00 2 LSBs of the 10-bit Right Auxiliary Volume
Function
12.15 Mute
MUTE_SOFTWARE
Address: F1h Type: R/W Bit 7 HP_D_MUTE Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 C_D_MUTE Bit 0 LS_D_MUTE
Soft Mute Output by DSP
SPDIF_D_MUT SCART2_D_M SCART1_D_M SRND_D_MUT SUB_D_MUTE E UTE UTE E
Bit Name
Reset
1 Digital Soft Mute for HP output: 0: 1: 1 Soft Mute not active Soft Mute active
Function
HP_D_MUTE
Digital Soft Mute for SPDIF output: 0: 1: Soft Mute not active Soft Mute active
SPDIF_D_MUTE
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Register List
STV82X8
Bit Name
Reset
1 Digital Soft Mute for SCART2 output: 0: 1: 1 Soft Mute not active Soft Mute active
Function
SCART2_D_MUTE
Digital Soft Mute for SCART1 output: 0: 1: Soft Mute not active Soft Mute active
SCART1_D_MUTE
1 SRND_D_MUTE
Digital Soft Mute for SURROUND output: 0: 1: Soft Mute not active Soft Mute active
1 SUB_D_MUTE
Digital Soft Mute for SUBWOOFER output: 0: 1: Soft Mute not active Soft Mute active
1 C_D_MUTE
Digital Soft Mute for CENTER output: 0: 1: Soft Mute not active Soft Mute active
1 LS_D_MUTE
Digital Soft Mute for LOUDSPEAKER output: 0: 1: Soft Mute not active Soft Mute active
12.16 Beeper
BEEPER_ON
Address: F2h Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 Bit 1 Bit 0 BEEPER_ON
Set Beeper On
BEEPER_SOUND_SELECT[ 1:0]
Bit Name
Bits[7:3]
Reset
00000 00 Reserved.
Function
Select the kind of sound generated by the beeper when BEEPER_ON is set to 1: 00: 01: 10: 11: Square Wave Signal. Frequency and Decay can be set in Register 0xf4. Wood Block Natural Sound Clic Natural Sound Bleep Natural Sound.
BEEPER_SOUND_ SELECT[1:0]
0 BEEPER_ON
Control Beeper Sound Start/Stop: 0: 1: Start Beeper Stop Beeper
Note:
if BEEPER_SOUND_SELECT = 0 and BEEPER_CONTINUOUS(reg 0xF3) is set to 1, the BEEPER_ON needs to be set to 0 to stop the beeper sound ; otherwise, the beeper is stopped automaticaly.
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STV82X8
Register List
On beeper STOP, the register 0xF2 is reset to 0. Take care to set bit[2:1] on each BEEPER_ON action.
BEEPER_MODE
Address: F3h Type: R/W Bit 7 Bit 6 BEEPER_DECAY[2:0] Bit 5
Beeper Control
Bit 4
Bit 3
Bit 2 BEEPER_CO NTINUOUS
Bit 1
Bit 0
BEEPER_DURATION[1:0]
BEEPER_PATH
Bit Name
BEEPER_DECAY [ 2:0]
Reset
Function
Control the decay of the envelope of the Beeper sound:
000
000: ... 111:
Short Decay (sounds dry) Very Long Decay (sounds wet)
BEEPER_DURATIO N [1:0] 00
Define Beeper Duration when BEEPER_CONTINUOUS is set to 0: 00: 01: 10: 11: 0.1 sec. 0.25 sec. 0.5 sec. 1 sec.
BEEPER_CONTIN UOUS
Set Beeper Pulse Mode 0 0: 1: Pulse mode selected, the BEEPER_ON is automaticaly reset to 0. Continuous mode selected, the BEEPER_ON must be set to 0 to stop the beeper sound.
BEEPER_PATH [ 1:0] 11
Set the output channels when beeper is active 00: 01: 10: 11: no channels. Loudspeakers only. Headphone only. Loudspeakers and Headphone selected.
BEEPER_FREQ_VOL
Address: F4h Type: R/W Bit 7 Bit 6 BEEP_FREQ[2:0] Bit 5
Beeper Frequency and Volume Settings
Bit 4
Bit 3
Bit 2 BEEP_VOL[4:0]
Bit 1
Bit 0
Bit Name
BEEP_FREQ[2:0]
Reset
011
Function
Defines the frequency of the beeper tone from 62.5 Hz to 8 kHz in octaves 000: 001: 010: 011: 62.5 Hz 125 Hz 250 Hz 500 Hz (Default) 100: 101: 110: 111: 1 kHz 2 kHz 4 kHz 8 kHz
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Register List
STV82X8
Bit Name
BEEP_VOL[4:0]
Reset
10000
Function
Defines the Beeper volume from 0 to -93 dB in steps of 3 dB. 11111: 11110: 11101: ... 10000: 0 dB (1 VRMS) -3 dB -6 dB -48 dB (Default) ... 00011: 00010: 00001: 00000: -84 dB -87 dB -90 dB -93 dB
12.17 SPDIF Output Configuration
SPDIF_OUT_CHANNEL_STATUS
Address: F5h Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 Bit 1 Bit 0
SPDIF_COPY SPDIF_NO_PC SPDIF_CONS RIGHT M UMER_PRO
Bit Name
Bits[7:3] SPDIF_COPYRIGH T SPDIF_NO_PCM SPDIF_CONSUME R_PRO
Reset
00000 0 0 0 Reserved. 0: 1: 0: 1: 0: 1: Copyright No Copyright PCM Format No PCM Format Consumer Format Professional Format
Function
12.18 Headphone Configuration
HEADPHONE_CONFIG
Address: F6h Type: R/W Bit 7 0 Bit 6 KARAOKE_MI X Bit 5 Bit 4 Bit 3 HP_FORCE Bit 2 HP_LS_MUTE Bit 1 Bit 0
Headphone Configuration
SCART2_OUT_SELECT[1:0]
HP_DET_ACTI HP_DETECTE VE D
Bit Name
Bits [7] KARAOKE_MIX
Reset
0 0 Reserved.
Function
When set, mix the HP channel signal with the LS channel signal. The mixed signal is output on the LS channel.
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STV82X8
Register List
Bit Name
Reset
Select SCART2 output:
Function
SCART2_OUT_SE LECT[1:0]
00
00: 01: 10: 11: 1:
SCART2 not output SCART2 signal output on C/Sub DAC SCART2 signal output on Srnd/HP DAC not used force to output the HP signal (bypass surround)
HP_FORCE
0
Note: when HP is forced, IRQ5 and HP/Srnd DAC automatic mute are not active. 0: 1: when HP is detected and active, LS are not muted when HP is detected and active, LS are muted
HP_LS_MUTE
0
HP_DET_ACTIVE HP_DETECTED
1 0
0: HP detection is not active 1: HP detection is active, when HP detected, Surround signal is bypassed and HP signal is outputed on HP 1: When a signal is detected on HP_DET pin
12.19 DAC Control
DAC_CONTROL
Address: F7h Type: R/W Bit 7 0 Bit 6 0 Bit 5 SPDIF_MUX Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POWER_UP
DAC Control Register
DAC_SCART_ DAC_SHP_MU DAC_CSUB_M DAC_LSLR_M MUTE TE UTE UTE
Bit Name
Bits [7:6]
Reset
00 Reserved.
Function
Redirect external or internal source i2s to i2s output : SPDIF_MUX 0 0: 1: Internal IS External IS
DAC_SCART_MUT E
SCART Left/Right Analog Soft Mute 1 0: 1: Soft Mute not active Soft Mute active
Surround/HP Left/Right Analog Soft Mute DAC_SHP_MUTE 1 0: 1: Soft Mute not active Soft Mute active
Center/Subwoofer Analog Soft Mute DAC_CSUB_MUTE 1 0: 1: Soft Mute not active Soft Mute active
LS Left/Right Analog Soft Mute DAC_LSLR_MUTE 1 0: 1: 0: 1: Soft Mute not active Soft Mute active DACs Power OFF Power ON
POWER_UP
1
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Register List DAC_SW_CHANNELS
Address: F8h Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
STV82X8 DAC SW Channel Register
Bit 0 SPDIF_SW
C_SUB_SW
SUR_HP_SW
SCART_SW
Bit Name
Reset
Center/Sub DAC:
Function
C_SUB_SW
00
00: Left/Right channels inverted 11: Left/Right channels non inverted Surround/HP DAC:
SUR_HP_SW
00
00: Left/Right channels inverted 11: Left/Right channels non inverted SCART DAC:
SCART_SW
00
00: Left/Right channels inverted 11: Left/Right channels non inverted SPDIF:
SPDIF_SW
00
00: Left/Right channels inverted 11: Left/Right channels non inverted
SPDIF_SW_CHANNELS
Address: F9h Type: R/W Bit 7 0 Bit 6 0 Bit 5 0
SPDIF SW Channel Register
Bit 4 0
Bit 3
Bit 2
Bit 1
Bit 0
DELAY_SW
LS_L_R_SW
Bit Name
Bits [7:4]
Reset
0000 00 Reserved. Delay output: 00: Left/Right channels inverted 11: Left/Right channels non inverted 00 Loudspeaker L/R output: 00: Left/Right channels inverted 11: Left/Right channels non inverted
Function
DELAY_SW
LS_L_R_SW
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STV82X8
Register List
12.20 AutoStandard Coefficients Settings
AUTOSTD_COEFF_CTRL
Address: FBh Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 Bit 0
Autostd Control Register Coefficients
AUTOSTD_COEFF_CTRL[1:0]
Bit Name
Bits [7:2]
Reset
000000 Reserved. Control the Demod filter coeff table settings 01: init Coeffs to ROM values 10: Update Coeffs with I2C value
Function
AUTOSTD_COEFF 01 _CTRL[1:0]
AUTOSTD_COEFF_INDEX_MSB
Address: FCh Type: R/W Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 AUTOSTD_CO EFF_INDEX_ MSB
Bit Name
Bits [7:2] AUTOSTD_COEFF _INDEX_MSB
Reset
0000000 Reserved. 0 FIR Coefficients table index (MSB)
Function
AUTOSTD_COEFF_INDEX_LSB
Address: FDh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
AUTOSTD_COEFF_INDEX_LSB[7:0]
Bit Name
AUTOSTD_COEFF _INDEX_LSB[7:0]
Reset
0000 0000 FIR Coefficients table index (LSB)
Function
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Register List AUTOSTD_COEFF_VALUE
Address: FEh Type: R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
STV82X8
Bit 0
AUTOSTD_COEFF_VALUE[7:0]
Bit Name
AUTOSTD_COEFF _VALUE[7:0]
Reset
0000 0000 FIR Coefficients table value to update
Function
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STV82X8
Pin Descriptions
13
13.1
Pin Descriptions
TQFP 80-pin Package

AP DP I O OD B A
= Analog Power = Digital Power = Input = Output = Open-Drain = Bi-Directional = Analog
Table 21: TQFP80 Pin Description (Sheet 1 of 4)
Pin No.
1 2 3 4 5 6 7 8 9 10
STV82X8 Pin Name
SC1_OUT_L SC1_OUT_R VCC_H GND_H SC3_OUT_L SC3_OUT_R VCC33_SC GND33_SC SC1_IN_L SC1_IN_R
Type (STV82X8)
A A AP AP A A AP AP A A
Function for STV82X8 (Function for STV82x6 in italic characters)
SCART1 Audio Output Left SCART1 Audio Output Right 8V Power for Audio I/O & ESD High Current Ground for Audio Outputs SCART3 Audio Output Left SCART3 Audio Output Right 3.3V Power for Audio Buffers & DAC / ADC Ground for Audio Buffers & DAC / ADC SCART1 Audio Input Left SCART1 Audio Input Right Audio Bias Voltage Decoupling 1.55V (Switched VREF decoupling pin for Audio Converters (VMCP)) AO1L
STV82x6 Pin Name
AO1R Not connected Connected to Ground Not connected Not connected VDDC GNDC AI1L AI1R
11
VREFA NC (GND_SA in
A
VMC1
12
STV82x7)
VBG SC2_IN_L SC2_IN_R VCC33_LS GND33_LS SC2_OUT_L SC2_OUT_R GND_SA (VCC_NISO in STV82x7)
AP Bandgap Voltage Reference Decoupling 1.2V (VREF decoupling pin for Audio Converters (VMC)) SCART 2 Audio Input Left SCART 2 Audio Input Right 3.3V Power for Audio DACs (3.3V Power Supply for Audio Buffers and SCART) Ground for Audio DACs (Ground for Audio Buffers and SCART) SCART 2 Audio Output Left SCART 2 Audio Output Right Ground for DACs
Connected to Ground
13 14 15 16 17 18 19 20
A A A AP AP A A AP
VMC2 AI2L AI2R VDDA GNDAH AO2L AO2R VDDH
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Pin Descriptions
Table 21: TQFP80 Pin Description (Sheet 2 of 4) Pin No.
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51
STV82X8
STV82X8 Pin Name
VSS33_CONV VDD33_CONV SC3_IN_L SC3_IN_R SCL_FLT SCR_FLT LS_C LS_L LS_R LS_SUB HP_LSS_L HP_LSS_R VSS18_CONV VDD18_CONV HP_DET ADR_SEL VSS18 VDD18 SCL SDA VSS18 VDD18 RST_N S/PDIF_IN S/PDIF_OUT VDD33_IO1 VSS33_IO1 CK_TST_CTRL VSS18 VDD18 CLK_SEL
Type (STV82X8)
AP AP A A A A A A A A A A DP DP I I DP DP OD OD DP DP I I O DP DP D DP DP I
Function for STV82X8 (Function for STV82x6 in italic characters)
Ground for DAC 1.8 to 3.3V Converters 3.3V Power for DAC 1.8 to 3.3V Converters (Voltage Reference for Audio buffers) SCART 3 Audio Input Left SCART 3 Audio Input Right SCART Filtering Left SCART Filtering Right (Bandgap Voltage Source Decoupling) Center Output Left Loudspeaker Output Right Loudspeaker Output Subwoofer Output Left Headphone Output or Left Surround Output Right Headphone Output or Right Surround Output Ground for Digital part of the DAC/ADC (Substrate Analog/Digital Shield) 1.8V Power for Digital part of the DAC/ADC Headphone Detection Hardware Address selection for IC Bus Ground for Digital part 1.8V Power for Digital part IC Clock Input IC Data I/O Ground for Digital part 1.8V Power for Digital part (5V Power Regulator Control) Main Reset Input Serial Audio Data Input (System Clock output) Serial Audio Data Output (IS Master Clock output) 3.3V power for Digital IO Ground for Digital IO To be Grounded Ground for Digital part 1.8V Power for Digital part Clock Input Format Selection
STV82x6 Pin Name
Connected to Ground VREFA AI3L AI3R Not connected BGAP Not connected LSL LSR SW HPL HPR GNDSA Not connected HPD ADR Connected to Ground Not connected SCL SDA Connected to Ground REG RESET SYSCK MCK VDD1 GND1 Not connected GNDSP Not connected Not connected
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STV82X8
Table 21: TQFP80 Pin Description (Sheet 3 of 4) Pin No.
52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79
Pin Descriptions
STV82X8 Pin Name
XTALIN_CLKXTP XTALOUT_CLKXTM VCC18_CLK1 GND18_CLK1 GND18_CLK2 VCC18_CLK2 VSS33_IO2 VDD33_IO2 I2S_PCM_CLK I2S_SCLK I2S_LR_CLK I2S_DATA0 I2S_DATA1 I2S_DATA2 VDD18 VSS18 BUS_EXP IRQ GND_PSUB VDD18_ADC VSS18_ADC SIF_P SIF_N GNDPW_IF VCC18_IF GND18_IF MONO_IN SC4_IN_L
Type (STV82X8)
I O AP AP AP DP DP DP I/O I/O I/O I/O I I DP DP O O AP DP DP A A AP AP AP A A
Function for STV82X8 (Function for STV82x6 in italic characters)
Crystal Oscillator Input or Differential Input Positive (Crystal Oscillator Input) Crystal Oscillator Output or Differential Input Negative (Crystal Oscillator Output) 1.8V Power for Clock PLL Analog & Crystal Oscillator 1/2 (3.3V Power supply for Analog PLL Clock) Ground for Clock PLL Analog & Crystal Oscillator 1/2 Ground for Clock PLL Digital 1/2 1.8V Power for Clock PLL Digital 1/2 (3.3V Power supply for Digital core, DSPs & IO Cells) Ground for Digital IO 3.3V power for Digital IO IS Master Clock Input/Output Channel 0, 1 & 2 IS Serial Clock Input/Output Channel 0, 1& 2 (IS bus data output) IS Word Select Input/Output Channel 0 , 1 & 2 (Stereo Detection output / IS Bus Data input) IS Data Input/Output Stereo Channel 0 (IS Bus Word Select output) IS Data Input Stereo Channel 1 (IS Bus Clock output) IS Data Input Stereo Channel 2 (Bus Expander Output 1) 1.8V Power for Digital Core & I/O Cells Pin Ground for Digital Core & I/O Cells Pin Bus Expander Function (Bus Expander Output 2) Interrupt Request to Microprocessor Ground Substrate Connection VDD 1.8V for ADC (Digital Part) Ground to Complement 1.8V VDD for ADC Sound IF input ADC VTOP Decoupling pin Polarization for the IF block (Voltage Reference for AGC Decoupling pin) 1.8V Power for IF AGC & ADC Ground for IF AGC & ADC Mono Input (for AM Mono) SCART4 Audio Input Left XTI XTO
STV82x6 Pin Name
VDDP GNDP GND2 VDD2 Connected to Ground Not connected Not connected SDO ST/SDI WS SCK BUS1 Not connected Connected to Ground BUS0 IRQ Connected to Ground Not connected Connected to Ground SIF VTOP VREFIF VDDIF GNDIF MONOIN Not connected
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Pin Descriptions
Table 21: TQFP80 Pin Description (Sheet 4 of 4) Pin No.
80
STV82X8
STV82X8 Pin Name
SC4_IN_R
Type (STV82X8)
A
Function for STV82X8 (Function for STV82x6 in italic characters)
SCART4 Audio Input Right
STV82x6 Pin Name
Not connected
13.2
TQFP 100-pin Package

AP DP I O OD B A
= Analog Power = Digital Power = Input = Output = Open-Drain = Bi-Directional = Analog
Table 22: TQFP100 Pin Description (Sheet 1 of 4)
Pin No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
STV82X8 Pin Name
SC1_OUT_L SC1_OUT_R VCC_H GND_H SC3_OUT_L SC3_OUT_R VCC33_SC GND33_SC SC1_IN_L SC1_IN_R VREFA VBG SC2_IN_L SC2_IN_R VCC33_LS GND33_LS SC2_OUT_L SC2_OUT_R SC5_IN_L SC5_IN_R NC
Type (STV82X8)
A A AP AP A A AP AP A A A A A A AP AP A A A A
Function for STV82X8
SCART1 Audio Output Left SCART1 Audio Output Right 8V Power for Audio I/O & ESD High Current Ground for Audio Outputs SCART3 Audio Output Left SCART3 Audio Output Right 3.3V Power for Audio Buffers & DAC / ADC Ground for Audio Buffers & DAC / ADC SCART1 Audio Input Left SCART1 Audio Input Right Audio Bias Voltage Decoupling 1.55V Bandgap Voltage Reference Decoupling 1.2V SCART 2 Audio Input Left SCART 2 Audio Input Right 3.3V Power for Audio DACs Ground for Audio DACs SCART 2 Audio Output Left SCART 2 Audio Output Right SCART 5 Audio Input Left SCART 5 Audio Input Right
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STV82X8
Table 22: TQFP100 Pin Description (Sheet 2 of 4) Pin No.
22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 NC GND_SA NC NC VSS33_CONV VDD33_CONV SC3_IN_L SC3_IN_R SCL_FLT SCR_FLT LS_C NC LS_L NC LS_R NC LS_SUB NC HP_LSS_L NC HP_LSS_R NC NC VSS18_CONV VDD18_CONV HP_DET ADR_SEL VSS18 VDD18 SCL SDA RST_N I2SD_DATA I2SO_DATA1 DP DP I I DP DP OD OD I I O Ground for Digital part of the DAC/ADC 1.8V Power for Digital part of the DAC/ADC Headphone Detection Hardware Address selection for IC Bus Ground for Digital part 1.8V Power for Digital part IC Clock Input IC Data I/O Main Reset Input IS Data Delay Input Stereo Channel IS Data Output Stereo Channel O_1 A A A Subwoofer Output A Right Loudspeaker Output A Left Loudspeaker Output AP AP A A A A A Ground for DAC 1.8 to 3.3V Converters 3.3V Power for DAC 1.8 to 3.3V Converters SCART 3 Audio Input Left SCART 3 Audio Input Right SCART Filtering Left SCART Filtering Right Center Output AP Ground for DACs
Pin Descriptions
STV82X8 Pin Name
Type (STV82X8)
Function for STV82X8
Left Headphone Output or Left Surround Output
Right Headphone Output or Right Surround Output
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Pin Descriptions
Table 22: TQFP100 Pin Description (Sheet 3 of 4) Pin No.
56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89
STV82X8
STV82X8 Pin Name
I2SO_LR_CLK I2SO_SCLK I2SO_DATAO S/PDIF_IN S/PDIF_OUT VDD33_IO1 VSS33_IO1 CK_TST_CTRL VSS18 VDD18 CLK_SEL XTALIN_CLKXTP XTALOUT_CLKXTM VCC18_CLK1 GND18_CLK1 GND18_CLK2 VCC18_CLK2 VSS33_IO2 VDD33_IO2 I2S_PCM_CLK I2S_SCLK I2S_LR_CLK I2S_DATA0 I2S_DATA1 I2S_DATA2 NC I2SA_SCLK I2SA_LR_CLK I2SA_DATA VDD18 VSS18 BUS_EXP IRQ GND_PSUB
Type (STV82X8)
O O O I O DP DP D DP DP I I O AP AP AP DP DP DP I/O I/O I/O I/O I I
Function for STV82X8
IS Word Select Output Channel O_0 & O_1 IS Serial Clock Output Channel O_0 & O_1 IS Data Output Stereo Channel O_0 Serial Audio Data Input Serial Audio Data Output 3.3V power for Digital IO Ground for Digital IO To be Grounded Ground for Digital part 1.8V Power for Digital part Clock Input Format Selection Crystal Oscillator Input or Differential Input Positive Crystal Oscillator Output or Differential Input Negative 1.8V Power for Clock PLL Analog & Crystal Oscillator 1/2 Ground for Clock PLL Analog & Crystal Oscillator 1/2 Ground for Clock PLL Digital 1/2 1.8V Power for Clock PLL Digital 1/2 Ground for Digital IO 3.3V power for Digital IO IS Master Clock Input/Output Channel 0, 1 & 2 IS Serial Clock Input/Output Channel 0, 1 & 2 IS Word Select Input/Output Channel 0,1 & 2 IS Data Input/Output Stereo Channel 0 IS Data Input Stereo Channel 1 IS Data Input Stereo Channel 2
I
IS Serial Clock Input Channel Auxiliary IS Word Select Input Channel Auxiliary IS Data Input Stereo Channel Auxiliary
DP DP O O AP
1.8V Power for Digital Core & I/O Cells Pin Ground for Digital Core & I/O Cells Pin Bus Expander Function Interrupt Request to Microprocessor Ground Substrate Connection
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STV82X8
Table 22: TQFP100 Pin Description (Sheet 4 of 4) Pin No.
90 91 92 93 94 95 96 97 98 99 100
Pin Descriptions
STV82X8 Pin Name
VDD18_ADC VSS18_ADC SIF_P SIF_N SIF2_P GNDPW_IF VCC18_IF GND18_IF MONO_IN SC4_IN_L SC4_IN_R
Type (STV82X8)
DP DP A A A AP AP AP A A A
Function for STV82X8
VDD 1.8V for ADC (Digital Part) Ground to Complement 1.8V VDD for ADC Sound IF input 1 ADC VTOP Decoupling pin Sound IF input 2 Polarization for the IF block 1.8V Power for IF AGC & ADC Ground for IF AGC & ADC Mono Input (for AM Mono) SCART 4 Audio Input Left SCART 4 Audio Input Right
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14
Application Diagrams
L17 * C69 33nF 100H L18 * C10 100nF 100H L14 * 100H L13 * 100H 1 L15 * 100H L16 * 100H C68 33nF C67 33nF C66 33nF C65 33nF C64 33nF
+1.8V
L2
10H
+ C9 330F
Headphone detection
1
+3.3V SL1
100nF C12
2
3 Address select C13
+ +
C63 33nF C62 33nF SC3 IN Right SC3 IN Left
3
+ +
SCL
100nF
Application Diagrams
SDA
C14 100nF
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
R1 R9 C75 220 R8 C74 220 C57 100nF 330pF
+ +
+3.3V 330pF
+
470K
C15
C16 470nF
Reset
100nF
SPDIF IN
SDA SCL VDD18 VSS18 ADR_SEL HP_DET VDD18_CONV VSS18_CONV HL_LSS_R HP_LSS_L LS_SUB LS_R LS_L LS_C SCR_FLT SCL_FLT SC3_IN_R SC3_IN_L VDD33_CONV VSS33_CONV
SPDIF OUT
+
L4 IC1 STV82X8 TQFP80
+3.3V
+
10H
+ C17 10F
C18 100nF
C19 100nF
+
C46 1F
+
10F C45 1F SC1 IN Right C47
+
R7 R6 C72 330pF C42 100nF R5 220 330pF C71 C70 330pF R4 220 + 10H L12 +8V
+
220 C73 330pF C44 100nF
+
C25 100nF 220
+1.8V C41 10F
C21
+
1.8V
C26 100nF
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 VSS18 VDD18 RST_N SPDIF_IN SPDIF_OUT VDD33_IO VSS33_IO CK_TST_CTRL VSS18 VDD18 CLK_SEL XTALIN/CLKXTP XTALOUT/CLKXTM VCC18_CLK1 GND18_CLK1 GND18_CLK2 VCC18_CLK2 VSS33_IO VDD33_IO I2S_PCM_CLK VCC_NISO SC2_OUT_R SC2_OUT_L GND33_LS VCC33_LS SC2_IN_R SC2_IN_L VBG GND_SA VREFA SC1_IN_R SC1_IN_L GND33_SC VCC33_SC SC3_OUT_R SC3_OUT_L GND_H VCC_H SC1_OUT_R SC1_OUT_L
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
27pF
C27
+
I2S_SCLK I2S_LR_CLK I2S_DATA0 I2S_DATA1 I2S_DATA2 VDD18 VSS18 BUS_EXP IRQ GND_PSUB VDD18_ADC VSS18_ADC SIF_P SIF_N GND_PWIF VCC18_IF GND18_IF MONO_IN SC4_IN_L SC4_IN_R
C22
XT1 27MHz CRYSTAL
100nF
+
1.8V
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
27pF
C37
+
+
R11 R11
L6 100nF L10 +1.8V 10H C34 22nF C29 100nF C30 100nF + +
Figure 31: STV82X8 TQFP80 Application Diagram
1.8V
C32 220nF C43 47F
10H
+ C23
10K
C33
47F
C35 IRQ
R3 560
L11
10H
STV82X8
Note : components with * are only mandatory in case of Dolby certification
+
+
+
+
+
+
+
138/157
C8 1F C7 1F C6 1F C5 1F C4 1F C3 1F C61 1F C60 1F C59 47F L1 10H +3.3V SC2 OUT Right SC2 OUT Left C56 10F C55 10F SC2 IN Right SC2 IN Left 100nF C51 10F C50 100nF C49 C53 1F C54 1F C52 SC1 IN Left 10F C48 10F SC3 OUT Right SC3 OUT Left SC1 OUT Right SC1 OUT Left C38 1F 1F R12 10K C36 1F SC4 IN Right SC4 IN Left Mono IN C40 10F C39 10F SIF 100pF BUS EXPANDER I2S DATA 2 I2S DATA 1 I2S DATA 0 I2S LR CLK I2S SCLK I2S PCM CLK
LS Center
LS Left
LS Right
Subwoofer
HP Left/LS surround Left
HP Right/LS surround Right
STV82X8
LS Center LS Left LS Right Subwoofer HP Left/LS surround Left HP Right/LS surround Right
+1.8V 10H L17 * + C9 330F C69 33nF 100H L18 * C10 100nF L14 * I2S0 DATA1 1 100H SL1 100H + C59 47F L1 10H +3.3V
+
L2
Headphone detection
C68 33nF
C67 33nF
C66 33nF
C65 33nF
100H
L16 * 100H
L15 * 100H
1
+3.3V 100nF C12
C79 1nF
L13 *
I2S0 LR CLK
2
3 Address select C62 33nF C13 100nF C63 33nF
I2S0 SCLK I2S PCM CLK
3
+
SCL
+
SDA R1 +3.3V C16 470nF IC1 Reset R9 220 470K
+
+ +
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
+
R8 220 C74 330pF C57 100nF
+
VDD18 VSS18 ADR_SEL HP_DET VDD18_CONV VSS18_CONV NC NC HP_LSS_R NC HP_LSS_L NC LS_SUB NC LS_R NC LS_L NC LS_C SCR_FLT SCL_FLT SC3_IN_R SC3_IN_L VDD33_CONV VSS33_CONV
+
external delay
+
STV82X8
C46
+
+ +
SPDIF IN C26 100nF L4 10H C19 100nF
10F 1F C45 1F SC1 IN Right SC1 IN Left
SPDIF OUT +3.3V
TQFP100
+ C17 10F C25 100nF
+
+
R7 220
C73 330pF R6 220 R5 220 R4 220 C71 330pF
+
+
+1.8V C21 +1.8V 27pF C22 +1.8V 27pF XT1 27MHz CRYSTAL C18 100nF C27 100nF
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 SCL SDA RST_N I2SD_DATA I2S0_DATA1 I2S0_LR_CLK I2S0_SCLK I2S0_DATA0 SPDIF_IN SPDIF_OUT VDD33_IO1 VSS33_IO1 CK_TST_CTRL VSS18 VDD18 CLK_SEL XTALIN_CLKXTP XTALOUT_CLKXTM VCC18_CLK1 GND18_CLK1 GND18_CLK2 VCC18_CLK2 VSS33_IO2 VDD33_IO2 I2S_PCM_CLK NC NC GND_SA NC NC SC5_IN_R SC5_IN_L SC2_OUT_R SC2_OUT_L GND33_LS VCC33_LS SC2_IN_R SC2_IN_L VBG VREFA SC1_IN_R SC1_IN_L GND33_SC VCC33_SC SC3_OUT_R SC3_OUT_L GND_H VCC_H SC1_OUT_R SC1_OUT_L
25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
C40 10F
+
I2S_SCLK I2S_LR_CLK I2S_DATA0 I2S_DATA1 I2S_DATA2 NC I2SA_SCLK I2SA_LR_CLK I2SA_DATA VDD18 VSS18 BUS_EXP IRQ GND_PSUB VDD18_ADC VSS18_ADC SIF_P SIF_N SIF2_P GNDPW_IF VCC18_IF GND18_IF MONO_IN SC4_IN_L SC4_IN_R
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
C42 100nF L12
+
C37 L6 +1.8V 10H + C23 47F C31 100nF + C36 C43 47F L10 10H +1.8V C34
560 10H +
+
R10
C35 SIF2 C32 220nF
L11
22nF C58 22nF
R3
C29 100nF
C33 100nF
100pF
C76 SIF1
R12 560
10K
Figure 32: STV82X8 TQFP100 Application Diagram
L19
10H
Note : components with * are only mandatory in case of Dolby certification
+
+ C64 33nF C61 1F C60 1F C20 100nF C78 1F C77 1F C75 330pF C56 10F C55 10F C53 1F C54 1F C52 100nF C51 10F C44 100nF C47 10F 10F C72 330pF C41 10F 10H +8V C38 1F 1F R11 1F 10K C39 10F C70 330pF 100pF
+
+
+
+
C8 1F
C7 1F
C6 1F
C5 1F
C4 1F
C3 1F
+
SC3 IN Right SC3 IN Left SC5 IN Right SC5 IN Left SC2 OUT Right SC2 OUT Left
SC2 IN Right SC2 IN Left C50 100nF C49
SC3 OUT Right C48 SC3 OUT Left
SC1 OUT Right SC1 OUT Left
SC4 IN Right SC4 IN Left Mono IN
IRQ BUS EXPANDER I2SA DATA I2SA LR CLK I2SA SCLK I2S DATA 2 I2S DATA 1 I2S DATA 0 I2S LR CLK I2S SCLK
Application Diagrams
139/157
Application Diagrams
L17 * + C9 330F L18 * C10 100nF L15 * 100H L14 * 100H SL1 100H L13 * 1 100H L16 * 100H C69 33nF C68 33nF 100H C67 33nF C66 33nF C65 33nF C64 33nF
+1.8V
L2
10H
Headphone detection
100nF C12
1
+3.3V
2
3 Address select C13 C62 33nF C63 33nF
3
+
+
SCL
100nF
SDA +3.3V
C14 100nF
R1
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
3
+3.3V C75
470K
C15
R9 220 330pF SL1 ( see Table 1) R8 C74 220 C57 100nF 330pF
+
C16 470nF
Reset
2
C58 100nF
+
100nF
SPDIF IN
1
+
SDA SCL VDD18 VSS18 ADR_SEL HP_DET VDD18_CONV VSS18_CONV HL_LSS_R HP_LSS_L LS_SUB LS_R LS_L LS_C SCR_FLT SCL_FLT SC3_IN_R SC3_IN_L VDD33_CONV VSS33_CONV
SPDIF OUT
+
L4 C19 100nF TQFP80 IC1 STV82x7 or STV82X8
+3.3V
+
10H
+ C17 10F
C18 100nF
+
C46 1F
10F
+ +
+
R7 220 C73 C72 330pF C42 100nF R5 220 330pF R4 220 C71 + + 10H L12 +8V C41 10F R6 220
C25 100nF
330pF
C44 100nF
+
+1.8V
C21
+
1.8V C27 100nF
C26 100nF
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 VSS18 VDD18 RST_N SPDIF_IN SPDIF_OUT VDD33_IO VSS33_IO CK_TST_CTRL VSS18 VDD18 CLK_SEL XTALIN/CLKXTP XTALOUT/CLKXTM VCC18_CLK1 GND18_CLK1 GND18_CLK2 VCC18_CLK2 VSS33_IO VDD33_IO I2S_PCM_CLK
+
VCC_NISO SC2_OUT_R SC2_OUT_L GND33_LS VCC33_LS SC2_IN_R SC2_IN_L VBG GND_SA VREFA SC1_IN_R SC1_IN_L GND33_SC VCC33_SC SC3_OUT_R SC3_OUT_L GND_H VCC_H SC1_OUT_R SC1_OUT_L
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
27pF
+
I2S_SCLK I2S_LR_CLK I2S_DATA0 I2S_DATA1 I2S_DATA2 VDD18 VSS18 BUS_EXP IRQ GND_PSUB VDD18_ADC VSS18_ADC SIF_P SIF_N GND_PWIF VCC18_IF GND18_IF MONO_IN SC4_IN_L SC4_IN_R
C22
XT1 27MHz CRYSTAL
C70 330pF C37 1F
+
1.8V
27pF
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
+
+
R11
L6 100nF L10 10H +
1.8V
C32 220nF C43 47F
10H
+ C23
+1.8V SIF C34 22nF C35 IRQ 100pF
47F
10K
C33
R3
560
10H
C29 100nF C30 100nF
L11
Figure 33: STV82x7/STV82X8 TQFP80 Compatiblity Application Diagram
STV82X8
Note : components with * are only mandatory in case of Dolby certification
+
+
+
+
+
+
+
140/157
Table 1 : SL1 configuration C8 1F STV82x7 : between 2 and 3 (pin 20 connected to 3.3V) STV82X8 : between 1 and 2 (pin 20 connected to ground) C7 1F C6 1F C5 1F C4 1F C3 1F SC3 IN Right SC3 IN Left C61 1F C60 1F C59 47F L1 10H SC2 OUT Right SC2 OUT Left C56 10F C55 10F SC2 IN Right SC2 IN Left 100nF C51 10F C50 100nF C49 C53 1F C54 1F C52 C45 1F SC1 IN Right C47 10F C48 10F SC1 IN Left SC3 OUT Right SC3 OUT Left SC1 OUT Right SC1 OUT Left C38 1F R12 10K C36 1F SC4 IN Right SC4 IN Left Mono IN C40 10F C39 10F BUS EXPANDER I2S DATA 2 I2S DATA 1 I2S DATA 0 I2S LR CLK I2S SCLK I2S PCM CLK
LS Center
LS Left
LS Right
Subwoofer
HP Left/LS surround Left
HP Right/LS surround Right
STV82X8
Input/Output Groups
15
Input/Output Groups
Pin numbers apply to SDIP package only.
VCC18_IF
VCC33_LS
VCC18_IF
SIF_P73
50K 50K
MONO_IN 78
30K
VREFA 50K GND_PSUB GND 33_LS
VCC_H
VCC18_IF
SC1_OUTL SC1_OUTR SC2_OUTL SC2_OUTR SC3_OUTL SC3_OUTR
1 2 5 6 18 19
VCC18_IF
SIF_N
74
REF
GND_PSUB
GNDIF
VCC33_LS
VCC_H
LS_L SCR_FLT LS_C LS_L LS_R LS_SUB HP_LSS_L HP_LSS_R
25 26 27 28 29 30 31 32
150
SC1_IN_L SC1_IN_R SC2_IN_L SC2_IN_R SC3_IN_L SC3_IN_R SC4_IN_L SC4_IN_R
9 10 14 15 23 24 79 80
VREFA
7K5 22K5
GND_PSUB
GND_PSUB
141/157
Input/Output Groups
STV82X8
VCC33_LS
VCC33_LS
VB G (1.2V)
10K
VREFA 11
5K4
VB G
13
BAND-GAP=1.2V
16K8
GND33_LS
GND33_LS
VDD33_I01
VDD33_I02
59
VCC18_CLK2 57 VCC18_CLK1 54 VDD33_I01 VDD18 46 38 42 50 66
HP_DET ADR_SEL RST_N CLK_TST_CTRL
35 36 43 48
VSS
VSS
37 41 47 49 58 67
VDD33_I01
VDD33_I01
GND18_CLK1 55
S/PDIF_OUT 45
GND18_CLK2 56
GND_PSUB
21 70
VSS
142/157
STV82X8
Input/Output Groups
VCC18_CLK1 VDD33_I02 VDD33_I02
XTALIN_CLKXTP BUS_EXD IRQ 68 69
52
GND18_CLK1 VCC18_CLK1 500K
VSS
XTALOUT_CLKXTM
53
VDD33_I01 GND18_CLK1
S/PDIF_IN
44
VDD18
VSS
CLK_SEL
51
VDD33_I02
VSS
I2S_PCM_CLK I2S_LR_CLK I2S_DATA0 I2S_DATA1 I2S_DATA2
60 61 62 63 64
VSS
SCL SDA
35 40
VSS
143/157
Input/Output Groups
STV82X8
VDD18_CONV VDD33_CONV VCC_NISO VCC33_LS VCC33_SC VCC_H VDD18_ADC VCC18_IF
34 22 20 16 7 3 71 76
GND18_IF
77
GNDPW_IF
75
VSS18_ADC
72
GND_PSUB
70 21
GND33_LS
17
GND_H
4
GND33_SC
8
GND_SA
12
VSS18_CONV
33
144/157
STV82X8
Electrical Characteristics
16
Electrical Characteristics
Test Conditions: TOPER = 25 C, VCC_H = 8 V, VXX_18 = 1.8V, VXX_33 = 3.3V, crystal oscillator at 27 MHz, default register values for synthesizer, unless otherwise specified.
16.1
Absolute Maximum Ratings
Parameter
Analog and Digital 1.8 V Supply Voltage (VCC18_CLK1, VCC18_CLK2, VCC18_IF, VDD18, VDD18_CONV, VDD18_ADC) Analog and Digital 3.3 V Supply Voltage (VCC33_SC, VCC33_LS, VDD33_IO1, VDD33_IO2, VDD33_CONV, VCC_NISO) Analog Supply High Voltage (VCC_H) Capacitor 100 pF discharged via 1.5 k serial resistor (Human Body Model) Operating Ambient Temperature Storage Temperature 4.0 8.8 4 0, +70 -55 to +150 V V kV C C 2.5 V
Symbol
VXX_18
Value
Units
VXX_33 HVCC VESD TOPER TSTG
16.2
Thermal Data
Parameter
Junction-to-Ambient Thermal Resistance
Symbol
RthJA
Value
42
Units
C/W
16.3
Power Supply Data
Parameter
Analog and Digital 1.8 V Supply Voltage (VCC18_CLK1, VCC18_CLK2, VCC18_IF, VDD18, VDD18_CONV, VDD18_ADC) Analog and Digital 3.3 V Supply Voltage (VCC33_SC, VCC33_LS, VDD33_IO1, VDD33_IO2, VDD33_CONV, VCC_NISO) Analog Supply High Voltage (VCC_H) Current Consumption for Digital 1.8 V Supply (VCC18_CLK2, VDD18, VDD18_CONV, VDD18_ADC) Current Consumption for Digital 3.3 V Supply ( VDD33_IO1, VDD33_IO2) Current Consumption for Analog 1.8 V Supply (VCC18_CLK1, VCC18_IF) Current Consumption for Analog 3.3 V Supply (VCC33_SC, VCC33_LS, VDD33_CONV, VCC_NISO) Current Consumption for Analog Supply High Voltage (8 V) Total Power Dissipation 3.13 7.6 3.30 8.0 TBD TBD TBD TBD TBD TBD 3.47 8.4 V V mA mA mA mA mA mW 1.70 1.80 1.90 V
Symbol
VXX_18
Min.
Typ.
Max.
Units
VXX_33 HVCC IVDD18 IVDD33 IVCC18 IVCC33 IVCC_H PDTOT
145/157
Electrical Characteristics
STV82X8
16.4
Crystal Oscillator
Parameter
Crystal Series Resonance Frequency (at C21 = C22 = 27 pF load capacitor) Frequency Tolerance at 25 C Frequency Stability versus Temperature within a range from 0 to 70 C Motional Capacitor Serial Resistance Shunt Capacitance -30 -30
Symbol
fP DF/FP DF/FT C1 RS CS
Min.
Typ.
27
Max.
Units
MHz
+30 +30 15 30 7
ppm ppm fF pF
16.5
Analog Sound IF Signal
Parameter
SIF Frequency Flatness SIF Input Resistance SIF Input DC Level SIF Input Capacitance
Symbol
BANDSIF RINSIF DCINSIF CINSIF FM Carrier
Test Conditions
AGC_ERR at 0, frequency range from 4 to 7MHz
Min.
Typ.
Max.
Units
dB
60
72 0.9 3
85
k V pF
VSIFFM
SIF Input Sensitivity
SNR 40 dB RMS unweighted 20 Hz to 15 kHz Standard M/N 27 kHz FM Deviation 1 kHz Standard (FM50k)
TBD
VPP
1
5 120
kHz kHz
DFSIFFM
SIF Carrier Accuracy for FM
Shifted Standard (FM50k with DCO compensation)
AGC AGCstep AGCdyn IF AGC Step Relative Maximum Gain to Step 0 Valid from Step 21 to Step 31 1.4 29 1.5 30 1.6 31 dB dB
16.6
SIF to IS Output Path Characteristics
Test Conditions: SIF amplitude = 100 mVpp, unless otherwise specified, IS output.
Symbol
FM Demodulation BANDFM
Parameter
Test Conditions
Min.
Typ.
Max.
Units
Frequency Response
20 Hz to 15 kHz
TBD
dB
146/157
STV82X8
Electrical Characteristics
Symbol
SNRFM THDFM SEPFM
Parameter
Signal to Noise Total Harmonic Distortion Stereo Channel Separation
Test Conditions
RMS unweighted, 20 Hz to 15 kHz, Standard M/N 27 kHz FM Deviation,1 kHz Standard M/N BTSC stereo, FM deviation, 1 kHz
Min.
TBD
Typ.
Max.
Units
dB
TBD TBD
% dB
16.7
SCART to SCART Analog Path Characteristics
Test Conditions: RloadMAX = 10 k CloadMAX = 330 pF, MONO_IN voltage = 0.5 VRMS ,
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Units
Analog-to-Analog STEREO and MONO RINSCART ROUTSCART VDCINSCART SCART Input Resistance Output Resistance for SCARTs SCART Input DC Level 34 40 1.57 3.64 k V V VRMS At 1 kHz 1% THD Clipping input level from MONO_IN input THD from SCART input 1 VRMS, at 1 KHz THDSCART THD SCART THD from MONO_IN input SCART input SNRSCART Signal to Noise Ratio MONO_IN input Frequency Flatness SCART input MONO_IN input 0.25 VRMS, at 1 KHz 1 VRMS, 20 Hz to 20 kHz Bandwidth, RMS unweighted 0.25 VRMS, 20 Hz to 20 kHz Bandwidth, RMS unweighted 20 Hz to 20 kHz 20 Hz to 20 kHz 1 VRMS @ 1 kHz on ref signal, the other one grounded 1 VRMS @ 1 kHz on ref signal, all other inputs grounded 1 VRMS @ 1 kHz on reference output, signal on a single input, all other inputs grounded 12 90 0.02 0.02 82 VRMS % % dB
VDCOUTSCART SCART Output DC Level Clipping input level from SCART input
CLIPSCART
Clipping SCART
76
dB dB dB dB
BANDSCART
XTALKL/R XTALKIN
Left/Right Crosstalk Audio Crosstalk from Input Channel n to Input Channel m Audio Crosstalk from Output Channel n to Output Channel m
90
dB
XTALKOUT
90
dB
147/157
Electrical Characteristics
STV82X8
16.8
SCART and MONO IN to IS Path Characteristics
Test Conditions: Sampling Frequency = 32 kHz, Maximum MONO_IN voltage = 0.5 VRMS.
Symbol
Parameter
THD from SCART input
Test Conditions
VIN = 2 VRMS at 1 KHz
Min.
Typ.
0.006 0.006
Max.
Units
% % dB dB dB
THDADC
THD ADC THD from V = 0.5 VRMS at 1 KHz MONO_IN input IN
SNRADC BANDADC XTALKADC
Signal to Noise Ratio Frequency Flatness Left Right Crosstalk
20 to 15 kHz Bandwidth, RMS unweighted VIN = 200 mVRMS SCART input 20 Hz to 15 kHz at 1 KHz, VIN = 1 VRMS
16.9
I2S to LS/HP/SUB/C Path Characteristics
Test Conditions: Sampling Frequency = 32KHz, LLOAD = 100 H, CLOAD = 33nF, RLOAD = 30K.
Symbol
ROUTDAC VDCOUTDAC THDDAC SNRDAC
Parameter
Output Resistance for Main Outputs MAIN Output DC Level Total Harmonic Distortion Signal to Noise Ratio
Test Conditions
LS_L, LS_R, LS_SUB, LS_C, HP_LSS_R and HP_LSS_L pins
Min.
Typ.
90 1.54
Max.
Units
V % dB
90% Full-scale Range at 1 kHz 20 to 15 kHz Bandwidth, RMS unweighted, at -20dB full range 100% Full-scale Range at 1 kHz at 1 KHz, -20dBFS 900
VOUTAMPDAC MAIN Output Amplitude XTALKDAC Left Right Crosstalk
mVRMS dB
16.10 IS to SCART Path Characteristics
Test Conditions: Sampling Frequency = 32 kHz, CLOAD = 33 nF on DAC SCART pins, DAC SCART prescale at -5.5 dB.
Symbol
THDDACSCART SNRDACSCART VODACSCART
Parameter
Total Harmonic Distortion Signal to Noise Ratio MAIN Output Amplitude
Test Conditions
90% Full-scale Range at 1 kHz 20 Hz to 15 kHz Bandwidth unweighted, -20dB Full Range 100% Full-scale Range at 1 kHz at 1 KHz, -20 dBFS
Min.
Typ.
0.08
Max.
Units
% dB
2
VRMS dB
XTALKDACSCART Left Right Crosstalk
148/157
STV82X8
Electrical Characteristics
16.11 MUTE Characteristics
Symbol
MUTEDAC MUTESCART
Parameter
DAC Mute analog SCART Mute
Test Conditions
I2S to DAC at 1 kHz 2 VRMS @ 1 kHz on ref signal, all other inputs grounded
Min.
Typ.
Max.
Units
dB dB
16.12 Digital I/Os Characteristics
Symbol
V V
IL
Parameter
Low Level Input Voltage High Level Input Voltage Input Current CLK_SEL Low Level Input Voltage CLK_SEL High Level Input Voltage Low Level Output Voltage High Level Output Voltage
Test Conditions
except SDA, SCL and CLK_SEL, 3.3V power supply except SDA, SCL and CLK_SEL, 3.3V power supply
Min.
Typ.
Max.
0.5
Units
V V
IH
2.0 1
IIN VILCLK_SEL VIHCLK_SEL V V
A V
1.8V power supply
0.3
1.8V power supply S/PDIF_OUT, IRQ, BUS_EXP S/PDIF_OUT, IRQ, BUS_EXP
1.2 0.3 3.0
V V V
OL
OH
149/157
Electrical Characteristics
STV82X8
16.13 IC Bus Characteristics
Symbol
SCL VIL VIH IIL fSCL tR tF CI SDA VIL VIH IIL tR tF VOL tF CL CI IC Timing tLOW tHIGH tSU,DAT tHD,DAT tSU,STO tBUF tHD,STA tSU,STA Clock Low period Clock High period Data Set-up Time Data Hold Time Set-up Time from Clock High to Stop Start Set-up Time following a Stop Start Hold Time Start Set-up Time following Clock Low to High Transition 1.3 0.6 100 0 0.6 1.3 0.6 0.6 900 s s ns ns s s s s Low Level Input Voltage High Level Input Voltage Input Leakage Current Input Rise Time Input Fall Time Low Level Output Voltage Output Fall Time Load Capacitance Input Capacitance VIN = 0 to 5.0 V 1 V to 2 V 2 V to 1 V IOL = 3 mA 2 V to 1 V -0.3 2.3 -10 1.5 5.5 10 300 300 0.4 250 400 10 V V A ns ns V ns pF pF Low Level Input Voltage High Level Input Voltage Input Leakage Current Clock Frequency Input Rise Time Input Fall Time Input Capacitance 1 V to 2 V 2 V to 1 V VIN = 0 to 5.0 V -0.3 2.3 -10 1.5 5.5 10 400 300 300 10 V V A kHz ns ns pF
Parameter
Test Conditions
Min.
Typ
Max.
Unit
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STV82X8
Figure 34: IC Bus Timing
Electrical Characteristics
SDA
tBUF tLOW tSU,DAT
SCL tHD,STA tR tHD,DAT tHIGH tF tSU,STO
SDA
tSU,STA
16.14 IS Bus Interface
IS Bus Interface timing values shown in Figure 35.
Symbol
IS Input VI2S_IL VI2S_IH ZI2S II2S_Leak tI2S_Su tI2S_Ho Input IS Low Level Voltage Input IS High Level Voltage Input IS Impedance IS Leakage Current IS Input Setup Time before Rising Edge of Clock IS Input Hold Time after Rising Edge of Clock IS Left Right Strobe Input Frequency (IS_DATA0 and ISA_DATA with SRC) IS Serial Clock Input Frequency (IS_DATA0 and ISA_DATA with SRC) IS Left Right Strobe Input Frequency (IS_DATA0 and ISA_DATA with PLL, IS_DATA1,2) IS Serial Clock Input Frequency (IS_DATA0 and ISA_DATA with PLL, IS_DATA1,2) IS Serial Clock Input Ratio 0.9 See Figure 35 See Figure 35 -1 30 100 2 5 1 0.8 V V pF A ns ns
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
fI2S_LR0
30
49
kHz
fI2S_SCL0
1.092
3.136
MHz
fI2S_LR
Deviation = 250 ppm
32
48
kHz
fI2S_SCL
3.072
MHz
RI2S_SCL
1.1
IS Output (IS_DATA0 only) VI2SOL VI2SOH Output IS Low Level Voltage Output IS High Level voltage IOL = 2 mA IOH = 2 mA 2.4 0.4 V V
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Electrical Characteristics
STV82X8
Symbol
fI2S_OLR
Parameter
IS Left Right Strobe Output Frequency (IS_DATA0 and ISO_DATA0,1) IS Serial Clock Output Frequency (IS_DATA0 and ISO_DATA0,1) IS Serial Clock Output Ratio IS Output Delay After Falling Edge of Clock
Test Conditions
Min.
Typ.
48
Max.
Unit
kHz
fI2S_OSCL RI2S_SCL tI2S_DEL
3.072 0.9 See Figure 35, Cl = 30 pF 1.1 30
MHz
ns
Figure 35: IS Input Bus Timings
IS_SCLK tI2S_Su IS_DATA tI2S_Su IS_LR_CLK tI2S_Ho
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STV82X8
Package Mechanical Data
17
17.1
Package Mechanical Data
TQFP80 Package
Figure 36: 80-Pin Thin Plastic Quad Flat Package
D D1 A1
A A2
b
e E1 E
L1 L h
c
Table 23: Package Mechanical Dimensions mm Dim. Min.
A A1 A2 b C D D1 E E1 e K L L1 0 0.45 0.05 1.35 0.22 0.09 16.00 14.00 16.00 14.00 0.65 3.5 0.60 1.00 0.75 0.75 0 0.018 1.40 0.32
inches Max.
1.60 0.15 1.45 0.38 0.20 0.002 0.053 0.009 0.004 0.630 0.551 0.630 0.551 0.026 3.5 0.024 0.039 0.75 0.030 0.055 0.013
Typ.
Min.
Typ.
Max.
0.063 0.006 0.057 0.015 0.008
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Package Mechanical Data
STV82X8
17.2
TQFP100 Package
Figure 37: 100-Pin Thin Plastic Quad Flat Package
D D1
A A2
A1
b
e
E1
E
L1 L h
c
Table 24: Package Mechanical Dimensions mm Dim. Min.
A A1 A2 b C D D1 E E1 e 0.05 1.35 0.17 0.09 16.00 14.00 16.00 14.00 0.50 0 0.45 3.5 0.60 1.00 Number of Pins N 100 7 0.75 0 0.018 1.40 0.22
inches Max.
1.60 0.15 1.45 0.27 0.20 0.002 0.053 0.007 0.004 0.630 0.551 0.630 0.551 0.020 3.5 0.024 0.039 7 0.030 0.055 0.009
Typ.
Min.
Typ.
Max.
0.063 0.006 0.057 0.011 0.008
L L1
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STV82X8
Revision History
18
Revision History
Date
15 Nov. 2004 19 Nov. 2004 7 Jan. 2005 23 Feb. 2005 Preliminary Datasheet - First Issue. Major updates to Key Features on page 1, Typical Applications on page 1 and Chapter 1: General Description on page 8. Addition of TQFP100 information. Updated Figure 1: STV82X8 Block Diagram (TQFP80) on page 2, Figure 2: STV82X8 Block Diagram (TQFP100) on page 3, Section 16.5: Analog Sound IF Signal on page 146 and Section 16.6: SIF to IS Output Path Characteristics on page 146.
Revision
0.1 0.2 0.3 1.0
Modification
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Index
A
Analog-to-Digital Conversion ..................................... 19 Audio Matrix Analog ............................................................ 35 Automatic Frequency Control ..................................... 20 Automatic Gain Control ............................................ 19 Automatic Standard Recognition System ...........19-20, 47 TQFP 80 ......................................................... 37 TQFP100 ........................................................ 38 I2C .................................................................... 151 I2C Address ........................................................... 44 IRQ Generation ...................................................... 42
L
Loudness Control Automatic ........................................................ 32
B
Back-end Processing ............................................... 21 Bass Management .................................................. 25 Bass-Treble Control ................................................. 31 Beeper ................................................................. 33
P
Package Mechanical Data ....................................... 153 Power Supply Management ....................................... 41
C
Clock Generator
R
Registers Clocking 1 ....................................................... 56 Clocking 2 ....................................................... 72 Demodulator .................................................... 58 Demodulator Channel 1 ...................................... 61 General Control ................................................ 53 IC Map .......................................................... 47 Reset values .......................................................... 43
..................................................... 18
D
Demodulation ......................................................... 19 Dolby Pro Logic II Decoder ........................................ 25
E
Electrical Characteristics ........................................ 145 Absolute Maximum Ratings ............................... 145 Analog Sound IF Signal .................................... 146 Crystal Oscillator ............................................. 146 Digital I/Os .................................................... 149 IC Bus ......................................................... 150 I2S to LS/HP/SW Path ..................................... 148 I2S to SCART Path ......................................... 148 MUTE Performance ......................................... 149 SCART to LS/HP/SW Path ................................ 148 SCART to SCART Analog Path .......................... 147 SIF to LS/HP/SCART Path ................................ 146 Supply Data ................................................... 145 Thermal Data ................................................. 145 Equalizer 5-Band Audio ................................................... 31
S
SIF Signal Analog ............................................................ 19 Signal Processor Dedicated Digital ............................................... 21 Signal to Noise ..................................................... 147 Smart Volume Control .............................................. 30 Soft Mute Control .................................................... 33 Software Information ................................................ 14 SRS 3D Mono/Stereo ............................................... 30 Dialog Clarity ................................................... 30 WOW ............................................................. 30 SRS TruBass ....................................................... 30 TruSurround .................................................... 29 TruSurround XT ............................................. 29 ST Bass Enhancer .................................................. 31 ST Dynamic Bass ................................................... 31 ST OmniSurround ................................................... 25 ST WideSurround ................................................... 24
H
Headphone Detection
.............................................. 42
I
IC Address ........................................................... 44 IC Bus Expander ................................................... 42 IC Protocol ........................................................... 44 IS Inputs TQFP100 ........................................................ 37 TQFP80 .......................................................... 36 IS Outputs Total Harmonic Distortion
T
........................................ 147
V
Volume/Balance Control
........................................... 32
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STV82X8
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2005 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com
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